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Programmable Touch Controller for Single Electrode Capacitance Sensors
AD7148
FEATURES
Programmable capacitance-to-digital converter (CDC) Femtofarad (fF) resolution 8 capacitance sensor inputs 25 ms update rate, all 8 sensor inputs No external RC components required Automatic conversion sequencer On-chip automatic calibration logic Automatic compensation for environmental changes Automatic adaptive threshold and sensitivity levels Register map compatible with AD7143 On-chip RAM to store calibration data I2C-compatible serial interface Separate VDRIVE level for serial interface Interrupt output 16-lead, 4 mm x 4 mm LFCSP 2.6 V to 3.3 V supply voltage Low operating current Full power mode: 1 mA Low power mode: 21.5 A
FUNCTIONAL BLOCK DIAGRAM
ACSHIELD VCC
5 8
GND
7
BIAS
6
AD7148
CIN0 13 CIN1 14 CIN2 15 CIN3 16 CIN4 CIN5 CIN6 CIN7
1 2 3 4
EXCITATION SOURCE CALIBRATION RAM 16-BIT - CDC
POWER-ON RESET LOGIC
SWITCH MATRIX
CALIBRATION ENGINE
CONTROL AND DATA REGISTERS
SERIAL INTERFACE AND CONTROL LOGIC
INTERRUPT AND GPIO LOGIC
9
10
11
12
VDRIVE
SDA
SCLK
INT
APPLICATIONS
Cell phones Personal music and multimedia players Smart handheld devices Television, A/V, and remote controls Gaming consoles Digital still cameras
Figure 1.
GENERAL DESCRIPTION
The AD7148 is designed for use with capacitance sensors implementing functions such as buttons, scroll bars, and wheels. The sensors need only one PCB layer, enabling ultrathin applications. The AD7148 is an integrated capacitance-to-digital converter (CDC) with on-chip environmental calibration. The CDC has eight inputs channeled through a switch matrix to a 16-bit, 250 kHz sigma-delta (-) converter. The CDC is capable of sensing changes in the capacitance of the external sensors and uses this information to register a sensor activation. The external sensors can be arranged as a series of buttons, as a scroll bar or wheel, or as a combination of sensor types. By programming the registers, the user has full control over the CDC setup. High resolution sensors require minimal software to run on the host processor. The AD7148 is designed for single electrode capacitance sensors (grounded sensors). There is an active shield output to minimize noise pickup in the sensor. For floating, or two, electrode sensors, use the AD7143. The AD7148 has on-chip calibration logic to compensate for changes in the ambient environment. The calibration sequence is performed automatically and at continuous intervals as long as the sensors are not touched. This ensures that there are no false or nonregistering touches on the external sensors due to a changing environment. The AD7148 has an I2C(R)-compatible serial interface, as well as an interrupt output. There is a VDRIVE pin to set the voltage level for the serial interface independent of VCC. The AD7148 is available in a 16-lead, 4 mm x 4 mm LFCSP and operates from a 2.6 V to 3.6 V supply. The operating current consumption in low power mode is typically 26 A.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
07155-001
AD7148 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Typical Average Current in Low Power Mode ......................... 4 Maximum Average Current in Low Power Mode.................... 4 I C Timing Specifications (AD7148-1) ..................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 10 Capacitance Sensing Theory..................................................... 10 BIAS Pin....................................................................................... 11 Operating Modes........................................................................ 11 Capacitance-to-Digital Converter................................................ 13 Oversampling the CDC Output ............................................... 13 Capacitance Sensor Offset Control.......................................... 13 Conversion Sequencer ............................................................... 13 CDC Conversion Sequence Time ............................................ 14 CDC Conversion Results........................................................... 15 Capacitance Sensor Input Configuration.................................... 16 CINx Input Multiplexer Setup .................................................. 16 Single-Ended Connections to the CDC .................................. 16 Noncontact Proximity Detection ................................................. 17 Recalibration ............................................................................... 18
2
Proximity Sensitivity.................................................................. 20 FF_SKIP_CNT............................................................................ 20 Environmental Calibration ........................................................... 22 Capacitance Sensor Behavior Without Calibration............... 22 Capacitance Sensor Behavior with Calibration...................... 22 SLOW FIFO ................................................................................ 23 SLOW_FILTER_UPDATE_LVL .............................................. 23 Adaptive Threshold and Sensitivity ............................................. 24 Interrupt Output............................................................................. 26 CDC Conversion-Complete Interrupt .................................... 26 Sensor Touch Interrupt.............................................................. 26 ACSHIELD Output .............................................................................. 27 I2C-Compatible Serial Interface ................................................... 28 VDRIVE Input ................................................................................. 30 PCB Design Guidelines ................................................................. 31 Capacitive Sensor Board Mechanical Specifications ............. 31 Chip Scale Packages ................................................................... 31 Power-Up Sequence ....................................................................... 32 Typical Application Circuit ........................................................... 33 Register Map ................................................................................... 34 Detailed Register Descriptions ..................................................... 35 Bank 1 Registers ......................................................................... 35 Bank 2 Registers ......................................................................... 43 Bank 3 Registers ......................................................................... 48 Outline Dimensions ....................................................................... 56 Ordering Guide .......................................................................... 56
REVISION HISTORY
12/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 56
AD7148 SPECIFICATIONS
VCC = 2.6 V to 3.6 V, TA = -40oC to +85C, unless otherwise noted. Table 1.
Parameter CAPACITANCE-TO-DIGITAL CONVERTER Update Rate Resolution CINx Input Range No Missing Codes Total Unadjusted Error Output Noise (Peak-to-Peak) Output Noise (RMS) CSTRAY Offset Range CSTRAY Offset Resolution Low Power Mode Delay Accuracy EXCITATION SOURCE Frequency Output Voltage ACSHIELD Short-Circuit Source Current Short-Circuit Sink Current Maximum Output Load LOGIC INPUTS (SCLK, SDA,) Input High Voltage, VIH Input Low Voltage, VIL Input High Voltage, IIH Input Low Voltage, IIL Hysteresis OPEN-DRAIN OUTPUTS (SCLK, SDA, INT) Output Low Voltage, VOL Output High Leakage Current, IOH POWER VCC VDRIVE ICC Min 24.25 Typ 25 16 8 16 20 7 3 0.8 0.5 20 0.32 4 250 0 10 10 150 0.7 x VDRIVE 0.4 -1 1 150 0.4 1 3.6 3.6 1 21.5 7.5 VCC Max 25.75 Unit ms Bits pF Bits % Codes Codes Codes Codes pF pF % kHz V mA mA pF V V A A mV V A V V mA A A Test Conditions/Comments 8 conversion stages in sequencer; decimation rate = 256
Guaranteed by design, not production tested Decimation rate = 128 Decimation rate = 256 Decimation rate = 128 Decimation rate = 256 6-bit DAC % of 200 ms, 400 ms, 600 ms, or 800 ms
Oscillating
Capacitance load on ACSHIELD to ground
VIN = VDRIVE VIN = GND
+0.1 2.6 1.65 3.3 0.9 15.5 2.3
ISINK = -1 mA VOUT = VDRIVE
Serial interface operating voltage In full power mode, VCC + VDRIVE Low power mode, converter idle, VCC + VDRIVE Full shutdown, VCC + VDRIVE
Rev. 0 | Page 3 of 56
AD7148
TYPICAL AVERAGE CURRENT IN LOW POWER MODE
VCC = 3.6 V, T = 25C, load of 50 pF, unless otherwise noted. Table 2.
Low Power Mode Delay 200 ms Decimation Rate 64 128 256 64 128 256 64 128 256 64 128 256 1 20.83 25.3 34.11 18.17 20.43 24.9 17.28 18.79 21.79 16.84 17.97 20.23 2 24.18 31.92 46.99 19.86 23.79 31.53 18.41 21.04 26.25 17.69 19.66 23.59 Current Values of Conversion Stages (A) 3 4 5 6 7 27.52 30.82 34.11 37.37 40.6 38.45 44.87 51.21 57.45 63.6 59.51 71.66 83.47 94.94 106.1 21.55 23.23 24.9 26.57 28.23 27.12 30.43 33.72 36.98 40.22 38.06 44.5 50.83 57.08 63.23 19.54 20.67 21.79 22.91 24.03 23.28 25.51 27.73 29.94 32.13 30.67 35.04 39.37 43.66 47.9 18.53 19.38 20.23 21.07 21.91 21.35 23.03 24.7 26.37 28.03 26.93 30.24 33.53 36.79 40.03 8 43.81 69.66 116.96 29.88 43.43 69.3 25.14 34.32 52.11 22.75 29.69 43.24
400 ms
600 ms
800 ms
MAXIMUM AVERAGE CURRENT IN LOW POWER MODE
VCC = 3.6 V, load of 50 pF, unless otherwise noted. Table 3.
Low Power Mode Delay 200 ms Decimation Rate 64 128 256 64 128 256 64 128 256 64 128 256 1 27.71 32.96 43.28 24.61 27.26 32.51 23.58 25.35 28.87 23.06 24.39 27.04 2 31.65 40.72 58.37 26.6 31.21 40.29 24.91 27.99 34.11 24.06 26.38 30.98 Current Values of Conversion Stages (A) 3 4 5 6 7 35.56 39.44 43.28 47.1 50.89 48.37 55.89 63.3 70.59 77.77 72.99 87.17 100.92 114.26 127.22 28.58 30.55 32.51 34.47 36.42 35.12 39 42.85 46.67 50.46 47.94 55.47 62.88 70.18 77.36 26.23 27.55 28.87 30.18 31.5 30.62 33.24 35.84 38.43 41 39.29 44.41 49.48 54.5 59.46 25.05 26.05 27.04 28.03 29.02 28.36 30.33 32.29 34.25 36.2 34.9 38.78 42.64 46.46 50.25 8 54.64 84.84 139.8 38.36 54.22 84.44 32.8 43.56 64.38 30 38.14 54.01
400 ms
600 ms
800 ms
Rev. 0 | Page 4 of 56
AD7148
I2C TIMING SPECIFICATIONS (AD7148-1)
TA = -40C to +85C, VDRIVE = 1.65 V to 3.6 V, VCC = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25C to ensure compliance. All input signals timed from a voltage level of 1.6 V. Table 4.
Parameter 1 fSCLK t1 t2 t3 t4 t5 t6 t7 t8 tR tF
1
Limit 400 0.6 1.3 0.6 100 300 0.6 0.6 1.3 300 300
Unit kHz max s min s min s min ns min ns min s min s min s min ns max ns max
Description Start condition hold time, tHD; STA Clock low period, tLOW Clock high period, tHIGH Data setup time, tSU; DAT Data hold time, tHD; DAT Stop condition setup time, tSU; STO Start condition setup time, tSU; STA Bus free time between stop and start conditions, tBUF Clock/data rise time Clock/data fall time
Guaranteed by design, not production tested.
I2C Timing Diagram
t2
SCLK
tR
tF
t1
t1 t5
SDA
t3 t4
t7
t6
STOP START
START
STOP
Figure 2. I2C Detailed Timing Diagram
Rev. 0 | Page 5 of 56
07155-002
t8
AD7148 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter VCC to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except Supplies1 ESD Rating (Human Body Model) Operating Temperature Range Storage Temperature Range Junction Temperature LFCSP Power Dissipation JA Thermal Impedance IR Reflow Peak Temperature Lead Temperature (Soldering, 10 sec)
1
Rating -0.3 V to +3.6 V -0.3 V to VCC + 0.3 V -0.3 V to VDRIVE + 0.3 V -0.3 V to VDRIVE + 0.3 V 10 mA 2.5 kV -40C to +105C -65C to +150C 150C 450 mW 135.7C/W 260C 0.5C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
200A
IOL
TO OUTPUT PIN
1.6V CL 50pF 200A IOH
07155-003
Figure 3. Load Circuit for Digital Output Timing Specifications
Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
Rev. 0 | Page 6 of 56
AD7148 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16 CIN3 15 CIN2 13 CIN0 14 CIN1
CIN4 1 CIN5 2 CIN6 3 CIN7 4
PIN 1 INDICATOR
12 INT 11 SCLK 10 SDA 9 VDRIVE
AD7148
TOP VIEW (Not to Scale)
ACSHIELD 5
BIAS 6
GND 7
VCC 8
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic CIN4 CIN5 CIN6 CIN7 ACSHIELD BIAS GND VCC VDRIVE SDA SCLK INT CIN0 CIN1 CIN2 CIN3 Description Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. CDC Active Shield Output. Connect to external shield. Bias Node for Internal Circuitry. Requires 10 nF capacitor to ground. Ground Reference Point for All Circuitry. Supply Voltage. Serial Interface Operating Voltage Supply. I2C Serial Data Input/Output. SDA requires pull-up resistor. Clock Input for Serial Interface. General-Purpose Open-Drain Interrupt Output. Programmable polarity; requires pull-up resistor. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input.
Rev. 0 | Page 7 of 56
07155-004
AD7148 TYPICAL PERFORMANCE CHARACTERISTICS
935 915
2.5
2.0
895 875 DECIMATION = 128 855 835 DECIMATION = 256 DECIMATION = 64
ICC (A)
07155-005
ICC (A)
1.5
1.0
0.5
07155-008
815 795 2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
0 2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
VCC (V)
VCC (V)
Figure 5. Supply Current vs. Supply Voltage
180 160 140 120 200ms
Figure 8. Shutdown Supply Current vs. Supply Voltage
70 60 50 40 30 800ms 800ms 20 10 0 2.5
200ms
I CC (A)
ICC (A)
100 80 60 40 20 0 2.5
400ms 600ms
400ms 600ms
07155-006
2.7
2.9
3.1 VCC (V)
3.3
3.5
3.7
2.7
2.9
3.1 VCC (V)
3.3
3.5
3.7
Figure 6. Low Power Supply Current vs. Supply Voltage, Decimation Rate = 256
0.12
Figure 9. Low Power Supply Current vs. Supply Voltage, Decimation Rate = 64
1150
0.10
200ms
1100
0.08
ICC (mA)
0.06
400ms 600ms
ICC (A)
1050
1000
0.04 800ms 0.02
07155-007
950
07155-010
0 2.5
2.7
2.9
3.1 VCC (V)
3.3
3.5
3.7
900
0
100
200
300
400
500
ACSHIELD CAPACITIVE LOAD (pF)
Figure 7. Low Power Supply Current vs. Supply Voltage Decimation Rate = 128
Figure 10. Supply Current vs. Capacitive Load on CIN
Rev. 0 | Page 8 of 56
07155-009
AD7148
58000 56000 54000 52000
CDC NOISE p-p (LSB)
160 140 120 100 80 60 40
07155-046
25mV 50mV
75mV 100mV
125mV 150mV
175mV 200mV
CDC CODE (d)
50000 48000 46000 44000 42000 40000
0
25 50 100 200 400 800 1600 3200 6400 12800 25600 51200 102400 204800 409600 819200 1640000
0
100
200
300
400
500
ACSHIELD CAPACITIVE LOAD (pF)
SINE WAVE FREQUENCY (Hz)
Figure 11. CDC Output Code vs. Capacitive Load on ACSHIELD
Figure 14. Power Supply Sine Wave Rejection, VCC = 3.6 V
960 940 3.6V
INPUT CAPACITANCE (pF)
35 30 25 20 15 10 5 0
920 900
ICC (A)
3.3V
880 860 840 820 800 780 -60 2.6V
07155-011
-40
-20
0
20
40
60
80
100
120
0
10000
20000
30000
40000
50000
60000
TEMPERATURE (C)
CDC OUTPUT CODE
Figure 12. Supply Current vs. Temperature
Figure 15. CDC Linearity, VCC = 3.3 V
12
10
8
ICC (A)
6 3.6V 4 3.3V 2.6V 2
07155-012
0 -45
-25
-5
15
35
55
75
95
115
135
TEMPERATURE (C)
Figure 13. Shutdown Supply Current vs. Temperature
Rev. 0 | Page 9 of 56
07155-014
07155-013
20
AD7148 THEORY OF OPERATION
The AD7148 is a capacitance-to-digital converter (CDC) with on-chip environmental compensation, intended for use in portable systems requiring high resolution user input. The internal circuitry consists of a 16-bit, - converter that converts a capacitive input signal into a digital value. There are eight input pins on the AD7148: CIN0 to CIN7. A switch matrix routes the input signals to the CDC. The result of each capacitance-to-digital conversion is stored in on-chip registers. The host subsequently reads the results over the serial interface. The AD7148 has an I2C interface, ensuring that the part is compatible with a wide range of host processors. The AD7148 interfaces with up to eight external capacitance sensors. These sensors can be arranged as buttons, scroll bars, wheels, or as a combination of sensor types. The external sensors consist of an electrode on a single or multiple layer PCB that interfaces directly to the AD7148. The AD7148 can be set up to implement any set of input sensors by programming the on-chip registers. The registers can also be programmed to control features such as averaging, offsets, and gains for each of the external sensors. There is an on-chip sequencer to control how each of the capacitance inputs is polled. The AD7148 has on-chip digital logic and 528 words of RAM that are used for environmental compensation. The effects of humidity, temperature, and other environmental factors can affect the operation of capacitance sensors. Transparent to the user, the AD7148 performs continuous calibration to compensate for these effects, allowing the AD7148 to give error-free results at all times. The AD7148 requires minimal companion software that runs on the host or other microcontroller to implement high resolution sensor functions, such as scroll bars or wheels. However, no companion software is required to implement buttons. Button sensors are implemented on chip, entirely in digital logic. The AD7148 can be programmed to operate in either full power mode or low power, automatic wake-up mode. The automatic wake-up mode is particularly suited for portable devices that require low power operation, providing the user with significant power savings and full functionality. The AD7148 has an interrupt output, INT, to indicate when new data has been placed into the registers. INT is used to interrupt the host on sensor activation. The AD7148 operates from a 2.6 V to 3.6 V supply and is available in a 16-lead, 4 mm x 4 mm LFCSP.
CAPACITANCE SENSING THEORY
The AD7148 measures capacitance changes from sensors where one plate is connected to ground. The sensor electrode on the PCB makes up one plate of a virtual capacitor. The other plate of the capacitor is the user's finger, which is grounded with respect to the sensor input. The AD7148 first outputs an excitation signal to charge the plate of the capacitor. When the user comes close to the sensor, the virtual capacitor is formed, with the user acting as the second capacitor plate.
PLASTIC COVER
SENSOR PCB
- ADC
MUX
16-BIT DATA
AD7148
Figure 16. Capacitance Sensing Method
A square wave excitation signal is applied to the CINx input during the conversion, and the modulator continuously samples the charge going through the CINx pin. The output of the modulator is processed via a digital filter, and the resulting digital data is stored in the CDC_RESULT_Sx registers for each conversion stage, located at Address 0x00B to Address 0x012.
Rev. 0 | Page 10 of 56
07155-0015
EXCITATION SIGNAL 250kHz
AD7148
Registering a Sensor Activation
When a user approaches a sensor, the total capacitance associated with that sensor changes and is measured by the AD7148. When the capacitance changes to such an extent that a set threshold is exceeded, the AD7148 registers this as a sensor activation. On-chip threshold limits are used to determine when sensor activation occurs. Figure 17 shows the change in CDC_RESULT_Sx that occurs when a user activates a sensor. The sensor is deemed to be active only when the value of CDC_RESULT_Sx is either greater than the value of STAGEx_HIGH_THRESHOLD or less than the value of STAGEx_LOW_THRESHOLD.
SENSOR ACTIVE (A)
CDC OUTPUT CODES
The memory requirements for the host depend on the sensor and are typically 10 kB of code and 600 bytes of data memory, depending on the sensor type.
SENSOR PCB
AD7148
SPI OR I2C
Figure 18. Three-Part Capacitance Sensing Solution
Analog Devices supplies the sensor PCB footprint design libraries to the customer and supplies any necessary software on an opensource basis.
STAGEx_HIGH_THRESHOLD CDC_RESULT_Sx AMBIENT OR NO-TOUCH VALUE
BIAS PIN
The BIAS pin (Pin 6) is connected internally to the bias node in the AD7148. To ensure correct operation of the AD7148, connect a 10 nF capacitor between the BIAS pin and ground. The voltage at the BIAS pin is VCC/2.
STAGEx_LOW_THRESHOLD SENSOR ACTIVE (B)
07155-016
OPERATING MODES
The AD7148 has three operating modes. Full power mode, in which the device is always fully powered, is suited for applications where power is not a concern (for example, game consoles that have an ac power supply). Low power mode, in which the part automatically powers down, is tailored to give significant power savings over full power mode and is suited for mobile applications where power must be conserved. In shutdown mode, the part shuts down completely. The POWER_MODE bits of the PWR_CONTROL register (Address 0x000[1:0]) set the operating mode on the AD7148. Table 7 shows the POWER_MODE settings for each operating mode. To put the AD7148 into shutdown mode, set the POWER_MODE bits to either 01 or 11. Table 7. POWER_MODE Settings
POWER_MODE Bits 00 01 10 11 Operating Mode Full power mode Shutdown mode Low power mode Shutdown mode
Figure 17. Sensor Activation Thresholds
In Figure 17, two different sensor activations are shown. Sensor Activate (A) occurs when a sensor is connected to the positive input of the converter. In this case, when a user activates the sensor, there is an increase in the CDC code, and the value of CDC_RESULT_Sx exceeds the value of STAGEx_HIGH_ THRESHOLD. Sensor Active (B) occurs when the sensor is connected to the negative input of the converter. In this case, when a user activates the sensor, there is a decrease in the CDC code, and the value of CDC_RESULT_Sx becomes less than the value of STAGEx_LOW_THRESHOLD. For each conversion stage, the STAGEx_HIGH_THRESHOLD and the STAGEx_LOW_THRESHOLD registers are in Register Bank 3. The values in these registers are updated automatically by the AD7148 due to its environmental calibration and adaptive threshold logic. At power-up, the values in the STAGEx_HIGH_THRESHOLD and STAGEx_LOW_THRESHOLD registers are the same as those in the STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW registers in Register Bank 2. The user must program the STAGEx_ OFFSET_HIGH and STAGEx_OFFSET_LOW registers on device power-up. See the Environmental Calibration section for more information.
The power-on default setting of the POWER_MODE bits is 00, full power mode.
Complete Solution for Capacitance Sensing
Analog Devices, Inc., provides a complete solution for capacitance sensing. The two main elements of the solution are the sensor PCB and the AD7148. If the application requires high resolution sensors such as scroll bars or wheels, software is required that runs on the host processor. No position algorithm is required for button sensors.
Full Power Mode
In full power mode, all sections of the AD7148 remain fully powered and converting at all times. While a sensor is being touched, the AD7148 processes the sensor data. If no sensor is touched, the AD7148 measures the ambient capacitance level and uses this data for the on-chip compensation routines. In full power mode, the AD7148 converts at a constant rate. See the CDC Conversion Sequence Time section for more information.
Rev. 0 | Page 11 of 56
07155-017
HOST PROCESSOR 1 MIPS 10kB ROM 600 BYTES RAM
AD7148
Low Power Mode
When in low power mode, the POWER_MODE bits are set to 10 upon device initialization. If the external sensors are not touched, the AD7148 reduces its conversion frequency, thereby greatly reducing its power consumption. The part remains in a reduced power state while the sensors are not touched. After a delay defined by the LP_CONV_DELAY bits (200 ms, 400 ms, 600 ms or 800 ms), the AD7148 performs a conversion and uses this data to update the compensation logic. When an external sensor is touched, the AD7148 begins a conversion sequence every 25 ms to read back data from the sensors. In low power mode, total current consumption is an average of the current used during a conversion and the current used while the AD7148 is waiting for the next conversion to begin. For example, when LP_CONV_DELAY is 400 ms, the AD7148 typically uses 0.85 mA current for 25 ms and 14 A for 400 ms during the conversion interval. Note that these conversion timings can be altered through the register settings. See the CDC Conversion Sequence Time section for more information. The time required for the AD7148 to transition from a full power state to a reduced power state after the user stops touching the external sensors is configurable. The PWR_DOWN_TIMEOUT bits in the AMB_COMP_CTRL0 register (Address 0x002[13:12]) control the time delay before the AD7148 transitions to the reduced power state after the user stops touching the sensors.
Low Latency from Touch to Response
In low power mode, the AD7148 remains in a low power state until proximity is detected on any one of the external sensors. When proximity is detected, the AD718 is automatically configured into the full power mode operation, thus converting each sequence every 36 ms. Using this method, the latency delay is minimized because the AD7148 is operating in full power mode by the time the user physically makes contact with a sensor.
AD7148 SETUP AND INITIALIZATION POWER_MODE = 10
NO
USER IN YES PROXIMITY TO SENSOR?
CONVERSION SEQUENCE EVERY LP_CONV_DELAY UPDATE COMPENSATION LOGIC DATA PATH
CONVERSION SEQUENCE EVERY 36ms FOR SENSOR READBACK
YES
USER IN PROXIMITY TO SENSOR?
NO
07155-018
PROXIMITY TIMER COUNT DOWN
TIMEOUT
Figure 19. Low Power Mode Operation
Rev. 0 | Page 12 of 56
AD7148 CAPACITANCE-TO-DIGITAL CONVERTER
The capacitance-to-digital converter on the AD7148 has a - architecture with 16-bit resolution. There are eight possible inputs to the CDC that are connected to the input of the converter through a switch matrix. The sampling frequency of the CDC is 250 kHz. The simplified block diagram in Figure 20 shows how to apply the STAGEx_OFFSET registers to null the offsets. The 6-bit POS_AFE_OFFSET and NEG_AFE_OFFSET bits program the offset DAC to provide 0.32 pF resolution offset adjustment over a range of 20 pF. Apply the positive and negative offsets to either the positive or the negative CDC input using the NEG_AFE_OFFSET and POS_AFE_OFFSET bits. This process is required only once during the initial capacitance sensor characterization.
+DAC (20pF RANGE) 6 POS_AFE_OFFSET
OVERSAMPLING THE CDC OUTPUT
The decimation rate, or oversampling ratio, is determined by the DECIMATION bits of the PWR_CONTROL register (Address 0x000[9:8]), as listed in Table 8. Table 8. CDC Decimation Rate
DECIMATION Bits 00 01 10 11 Decimation Rate 256 128 64 64 CDC Output Rate per Stage (ms) 3.072 1.536 0.768 0.768
POS_AFE_OFFSET_SWAP BIT CIN + 16
16-BIT _ CDC
The decimation process reduces the amount of noise present in the final CDC result. However, the higher the decimation rate, the lower the output rate per stage; thus, a trade-off is possible between a noise-free signal and speed of sampling.
Figure 20. Analog Front-End Offset Control
CONVERSION SEQUENCER
The AD7148 has an on-chip sequencer to implement conversion control for the input channels. Up to eight conversion stages can be performed in one sequence. Each of the eight conversion stages can measure the input from a different sensor. By using the Bank 2 registers, each stage can be uniquely configured to support multiple capacitance sensor interface requirements. For example, a slider sensor can be assigned to STAGE0 through STAGE7, or a button sensor can be assigned to STAGE0. For each conversion stage, the input mux that connects the CINx inputs to the converter can have a unique setting.
CAPACITANCE SENSOR OFFSET CONTROL
There are two programmable DACs on board the AD7148 to null the effect of any stray capacitances on the CDC measurement. These offsets are due to stray capacitance to ground. Best practice is to ensure that the CDC output for any stage is approximately equal to midscale (~32,700) when no sensor is active.
Rev. 0 | Page 13 of 56
07155-019
The decimation process on the AD7148 is an averaging process, during which a number of samples are taken, and the averaged result is output. Due to the architecture of the digital filter used, the number of samples taken (per stage) is equal to 3x the decimation rate. That is, 3 x 256 samples or 3 x 128 samples are averaged to obtain each stage result.
NEG_AFE_OFFSET_SWAP BIT
-DAC (20pF RANGE)
6
NEG_AFE_OFFSET
CINx_CONNECTION_SETUP BITS
AD7148
The AD7148 on-chip sequence controller provides conversion control, beginning with STAGE0. Figure 21 shows a block diagram of the CDC conversion stages and CINx inputs. A conversion sequence is defined as a sequence of CDC conversions starting at STAGE0 and ending at the stage determined by the value that is programmed using the SEQUENCE_STAGE_NUM bits in the PWR_CONTROL register (Address 0x000[7:4]). Depending on the number and type of capacitance sensors that are used, not all conversion stages are required. Use the SEQUENCE_ STAGE_NUM bits to set the number of conversions in one sequence, depending on the sensor interface requirements. For example, these bits are set to 0005 if the CINx inputs are mapped to only six stages. In addition, set the STAGEx_CAL_EN register according to the number of stages that are used.
STAGE7 STAGE6 STAGE5 STAGE4 STAGE3 STAGE2 STAGE1 STAGE0
The number of required conversion stages depends completely on the number of sensors attached to the AD7148. Figure 22 shows how many conversion stages are required for each sensor and how many inputs to the AD7148 each sensor requires. A button sensor generally requires one sequencer stage; however, it is possible to configure two button sensors to operate differentially. Only one button from the pair can be activated at a time; pressing both buttons together results in neither button being activated. This configuration requires one conversion stage (see Figure 22, B2 and B3). A wheel sensor requires eight stages, and a slider requires two stages. The result from each stage is used by the host software to determine user position on the slider or wheel. The algorithms that perform this process are available from Analog Devices, free of charge, on signing a software license.
CDC CONVERSION SEQUENCE TIME
The time required for one complete measurement for all eight stages by the CDC is defined as the CDC conversion sequence time. The SEQUENCE_STAGE_NUM and DECIMATION bits determine the conversion time, as shown in Table 9. For example, while operating with a decimation rate of 128, if the SEQUENCE_STAGE_NUM bits are set to 0005 for the conversion of six stages in a sequence, the conversion sequence time is 9.216 ms.
CIN0 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7
CO NV E
SWITCH MATRIX
CIN1
RS IO
NS
EQ
07155-020
Figure 21. CDC Conversion Stages
AD7148 SEQUENCER
STAGE0 + CDC - STAGE1
UE NC E
- 16-BIT ADC
AD7148 SEQUENCER
BUTTONS
B1 B2 B3
STAGE0 + CDC - STAGE1 + CDC -
+ CDC - STAGE1 + CDC - STAGE1 + CDC - STAGE1 + - CDC
WHEEL
AD7148 SEQUENCER
STAGE3
SLIDER
STAGE1 + CDC - STAGE1 + CDC - STAGE1 + CDC -
+ CDC - STAGE4 + CDC -
Figure 22. Sequencer Setup for Sensors
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07155-021
AD7148
Table 9. CDC Conversion Times for Full Power Mode
SEQUENCE_STAGE_NUM 0 1 2 3 4 5 6 7 Decimation = 64 0.768 1.536 2.304 3.072 3.84 4.608 5.376 6.144 Conversion Time (ms) Decimation = 128 1.536 3.072 4.608 6.144 7.68 9.216 10.752 12.288 Decimation = 256 3.072 6.144 9.216 12.288 15.36 18.432 21.504 24.576
Full Power Mode CDC Conversion Sequence Time
The full power mode CDC conversion sequence time for all eight stages is set by configuring the SEQUENCE_STAGE_NUM and DECIMATION bits, as outlined in Table 9. Figure 23 shows a simplified timing diagram of the full power CDC conversion time. The full power mode CDC conversion time, tCONV_FP, is set using Table 9.
tCONV_FP
07155-022
Table 10. LP_CONV_DELAY Settings
LP_CONV_DELAY Bits 00 01 10 11 Delay Between Conversions (ms) 200 400 600 800
CDC CONVERSION
CONVERSION SEQUENCE N
CONVERSION SEQUENCE N+1
CONVERSION SEQUENCE N+2
Figure 24 shows a simplified timing example of the low power CDC conversion time. As shown, the low power CDC conversion time is set by tCONV_FP and the LP_CONV_DELAY bits.
tCONV_LP
tCONV_FP LP_CONV_DELAY
07155-023
Figure 23. Full Power Mode CDC Conversion Sequence Time
Low Power Mode CDC Conversion Sequence Time with Delay
The frequency of each CDC conversion, while operating in the low power automatic wake-up mode, is controlled by using the LP_CONV_DELAY bits located at Address 0x000[3:2], in addition to the registers listed in Table 9. This feature provides some flexibility for optimizing the conversion time to meet system requirements vs. AD7148 power consumption. For example, maximum power savings is achieved when the LP_CONV_DELAY bits (Address 0x000[3:2] are set to 11. With a setting of 11, the AD7148 automatically wakes up, performing a conversion every 800 ms.
CDC CONVERSION
CONVERSION SEQUENCE N
CONVERSION SEQUENCE N+1
Figure 24. Low Power Mode CDC Conversion Sequence Time
CDC CONVERSION RESULTS
Certain high resolution sensors require the host to read back the CDC conversion results for processing. The registers required for host processing are located in the Bank 3 registers. The host processes the data readback from these registers using a software algorithm to determine position information. In addition to the results registers found in the Bank 3 registers, the AD7148 provides the 16-bit CDC output data directly, starting at Address 0x00B of the Bank 1 registers. Reading back the CDC 16-bit conversion data register allows for customer-specific application data processing.
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AD7148 CAPACITANCE SENSOR INPUT CONFIGURATION
Each input connection from the external capacitance sensors to the AD7148 converter can be uniquely configured by using the registers in Bank 2 (see Table 39 through Table 42). These registers are used to configure input pin connection setups, sensor offsets, sensor sensitivities, and sensor limits for each stage. Each sensor can be individually optimized. For example, a button sensor connected to STAGE0 can have different sensitivity and offset values from those of a button with a different function that is connected to a different stage.
SINGLE-ENDED CONNECTIONS TO THE CDC
A single-ended connection to the CDC is defined as having one CINx input connected to either the positive or the negative CDC input. A differential connection to the CDC is defined as having one CINx input connected to the positive CDC input and a second CINx input connected to the negative input of the CDC. When a single-ended connection to the CDC is made in any stage, the SE_CONNECTION_SETUP bits in the STAGEx_ CONNECTION_SETUP registers should be applied. These bits ensure that, during a single-ended connection to the CDC, the input paths to both terminals are matched. This matching of input paths, in turn, improves the power supply rejection of the converter measurement. Table 11. Application of SE_CONNECTION_SETUP Bits
Bit Values 00 01 10 11 Description Do not use. Single-ended connection. For this stage, there is one CINx connected to the positive CDC input. Single-ended connection. For this stage, there is one CINx connected to the negative CDC input. Differential connection. For this stage, there is one CINx connected to the negative CDC input and one CINx connected to the positive CDC input.
CINx INPUT MULTIPLEXER SETUP
The CINx_CONNECTION_SETUP register bits provide options for connecting the sensor input pins to the CDC (see Table 39 and Table 40). The AD7148 has an on-chip multiplexer to route the input signals from each pin to the input of the converter. Each input pin can be tied to either the negative or the positive input of the CDC, or it can be left floating. Each input can also be internally connected to the BIAS signal to help prevent cross coupling. If an input is not used, always connect it to BIAS. Connecting a CINx input pin to the positive CDC input results in an increase in CDC output code when the corresponding sensor is activated. Connecting a CINx input pin to the negative CDC input results in a decrease in CDC output code when the corresponding sensor is activated. The AD7148 performs a sequence of eight conversions. The multiplexer can have different connection settings for each of the eight conversions by using the CINx_CONNECTION_ SETUP bits. For example, CIN0 can be connected to the negative CDC input or left floating. The same holds true for all eight conversion stages. Two bits in each sequence stage register control the mux setting for the input pin, as shown in Figure 25.
If more than one CINx input is connected to either the positive or negative input of the converter for the same conversion, set SE_CONNECTION_SETUP = 11. For example, if CIN0 and CIN3 are connected to the positive input of the CDC, SE_CONNECTION_SETUP = 11.
CINx_CONNECTION _SETUP BITS CIN0 CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 00 01 10
CIN SETTING CINx FLOATING CINx CONNECTED TO NEGATIVE CDC INPUT CINx CONNECTED TO POSITIVE CDC INPUT CINx CONNECTED TO BIAS
+
CDC
-
07155-024
11
Figure 25. Input Mux Configuration Options
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AD7148 NONCONTACT PROXIMITY DETECTION
The AD7148 internal signal processing continuously monitors all capacitance sensors for noncontact proximity detection. This feature provides the ability to detect when a user is approaching a sensor, at which time all internal calibration is immediately disabled while the AD7148 is automatically configured to detect a valid contact. The proximity control register bits are described in Table 12. The FP_PROXIMITY_CNT and LP_PROXIMITY_CNT register bits (Address 0x002[11:4]) control the length of the calibration disable period after the user leaves the sensor and proximity is no longer active in full and low power modes. Table 12. Proximity Control Registers (See Figure 30)
Bits FP_PROXIMITY_CNT LP_PROXIMITY_CNT FP_PROXIMITY_RECAL LP_PROXIMITY_RECAL PROXIMITY_RECAL_LVL PROXIMITY_DETECTION_RATE Length 4 bits 4 bits 10 bits 6 bits 8 bits 6 bits Register Address 0x002[7:4] 0x002[11:8] 0x004[9:0] 0x004[15:10] 0x003[7:0] 0x003[13:8] Description Calibration disable time in full power mode. Calibration disable time in low power mode. Full power mode proximity recalibration time. Low power mode proximity recalibration time. Proximity recalibration level. This value, multiplied by 16, controls the sensitivity of Comparator 2 in Figure 30. Proximity detection rate. This value, multiplied by 16, controls the sensitivity of Comparator 1 in Figure 30.
The calibration is disabled during this time and is enabled again at the end of this period, provided that the user is no longer approaching, or in contact with, the sensor. Figure 26 and Figure 27 show examples of how these registers are used to set the full and low power mode calibration disable periods. The calibration disable period in full power mode is equal to FP_PROXIMITY_CNT x 16 x time taken for one conversion sequence in full power mode. The calibration disable period in low power mode is equal to LP_PROXIMITY_CNT x 4 x time taken for one conversion sequence in low power mode.
USER APPROACHES SENSOR HERE 12345
USER LEAVES SENSOR AREA HERE
tCONV_FP
CDC CONVERSION SEQUENCE (INTERNAL) 6 7 8 9 10 11 12 13 14 15 16
tCALDIS
PROXIMITY DETECTION (INTERNAL)
CALIBRATION (INTERNAL)
CALIBRATION DISABLED
CALIBRATION ENABLED
Figure 26. Full Power Mode Proximity Detection Example with FP_PROXIMITY_CNT = 1
USER APPROACHES SENSOR HERE
USER LEAVES SENSOR AREA HERE
CDC CONVERSION SEQUENCE (INTERNAL)
1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 1718 19 20 21 22 23 24 tCALDIS
tCONV_LP
PROXIMITY DETECTION (INTERNAL)
CALIBRATION (INTERNAL)
CALIBRATION DISABLED
CALIBRATION ENABLED
Figure 27. Low Power Mode Proximity Detection with LP_PROXIMITY_CNT = 4
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07155-026
NOTES 1. SEQUENCE CONVERSION TIME tCONV_LP = tCONV_FP + LP_CONV_DELAY 2. PROXIMITY IS SET WHEN USER APPROACHES THE SENSOR AT WHICH TIME THE INTERNAL CALIBRATION IS DISABLED. 3. tCALDIS = (tCONV_LP x LP_PROXIMITY_CNT x 4)
07155-025
AD7148
RECALIBRATION
In certain situations, the proximity flag can be set for a long period: for example, when a user hovers over a sensor for a long time. The environmental calibration on the AD7148 is suspended while proximity is detected, but changes may occur to the ambient capacitance level during the proximity event. This means that the ambient value stored on the AD7148 no longer represents the actual ambient value. In this case, even when the user has left the sensor, the proximity flag may still be set. This situation could occur if user interaction creates some moisture on the sensor, causing the new sensor ambient value to be different from the expected value. In this situation, the AD7148 automatically forces an internal recalibration, ensuring that the ambient values are recalibrated, regardless of how long the user hovers over a sensor. The recalibration ensures maximum sensor performance. The AD7148 recalibrates automatically when the measured CDC value exceeds the stored ambient value by an amount determined by the PROXIMITY_RECAL_LVL bits (Address 0x003[7:0]) for a set period of time, known as the recalibration timeout.
USER APPROACHES SENSOR HERE USER LEAVES SENSOR AREA HERE 16 MEASURED CDC VALUE > STORED AMBIENT BY PROXIMITY_RECAL _LVL 30
In full power mode, the recalibration timeout is controlled by FP_PROXIMITY_RECAL; in low power mode, the timeout is controlled by LP_PROXIMTY_RECAL. The recalibration timeout in full power mode is the value of the FP_PROXIMITY_RECAL multiplied by the time taken for one conversion sequence in full power mode. The recalibration timeout in low power mode is the value of the LP_PROXIMITY_RECAL multiplied by the time taken for one conversion sequence in low power mode. Figure 28 and Figure 29 show examples of how the FP_ PROXIMITY_RECAL and LP_PROXIMITY_RECAL register bits (Address 0x004[15:0]) control the timeout period before a recalibration while operating in the full power and low power modes. These figures show a user approaching a sensor, followed by the user leaving the sensor while the proximity detection remains active after the user leaves the sensor. The measured CDC value exceeds the stored ambient value by the amount set in the PROXIMITY_ RECAL_LVL bits for the entire timeout period. The sensor is automatically recalibrated at the end of the timeout period.
tRECAL tCONV_FP
CDC CONVERSION SEQUENCE (INTERNAL)
70
tCALDIS
PROXIMITY DETECTION (INTERNAL)
CALIBRATION (INTERNAL)
CALIBRATION DISABLED
RECALIBRATION TIME-OUT
CALIBRATION ENABLED
NOTES 1. SEQUENCE CONVERSION TIME tCONV_FP DETERMINED FROM TABLE 9. 2. tCALDIS = tCONV_FP x FP_PROXIMITY_CNT x 16. 3. tRECAL_TIMEOUT = tCONV_FP x FP_PROXIMITY_RECAL. 4. tRECAL = 2 x tCONV_FP .
Figure 28. Full Power Mode Proximity Detection with Forced Recalibration Example with FP_PROXIMITY_CNT = 1 and FP_PROXIMITY_RECAL = 40
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07155-027
RECALIBRATION COUNTER (INTERNAL)
tRECAL_TIMEOUT
AD7148
USER APPROACHES SENSOR HERE USER LEAVES SENSOR AREA HERE 16
tRECAL
MEASURED CDC VALUE > STORED AMBIENT BY PROXIMITY_RECAL _LVL 30 70
tCONV_LP
CDC CONVERSION SEQUENCE (INTERNAL)
PROXIMITY DETECTION (INTERNAL)
tCALDIS
CALIBRATION (INTERNAL)
CALIBRATION DISABLED
RECALIBRATION TIME-OUT
CALIBRATION ENABLED
RECALIBRATION (INTERNAL)
tRECAL_TIMEOUT
NOTES 1. SEQUENCE CONVERSION TIME tCONV_LP = tCONV_FP + LP_CONV_DELAY 2. tCALDIS = tCONV_LP x LP_PROXIMITY_CNT x 4 3. tRECAL_TIMEOUT = tCONV_FP x LP_PROXIMITY_RECAL 4. tRECAL = 2 x tCONV_LP
Figure 29. Low Power Mode Proximity Detection with Forced Recalibration Example with LP_PROXIMITY_CNT = 4 and LP_PROXIMITY_RECAL = 40
Rev. 0 | Page 19 of 56
07155-028
AD7148
PROXIMITY SENSITIVITY
The fast filter in Figure 30 is used to detect when someone is close to the sensor (proximity). Two conditions set the internal proximity detection signal, using Comparator 1 and Comparator 2. Comparator 1 detects when a user is approaching a sensor. The PROXIMITY_DETECTION_RATE bits (Address0x003[13:8]) controls the sensitivity of Comparator 1. For example, if PROXIMITY_DETECTION_RATE is set to 4, the Proximity 1 signal is set when the absolute difference between WORD1 and WORD3 exceeds (4 x 16) LSB codes. Comparator 2 detects when a user hovers over a sensor or approaches a sensor very slowly. The PROXIMITY_RECAL_LVL bits (Address 0x003[7:0]) control the sensitivity of Comparator 2. For example, if PROXIMITY_ RECAL_LVL is set to 75, the Proximity 2 signal is set when the absolute difference between the fast filter average value and the ambient value exceeds (75 x 16) LSB codes.
CDC 16 FP_PROXIMITY_CNT REGISTER 0x002 STAGEx_FF_WORD0 STAGEx_FF_WORD1 STAGEx_FF_WORD2 STAGEx_FF_WORD3 STAGEx_FF_WORD4 STAGEx_FF_WORD5 STAGEx_FF_WORD6 STAGEx_FF_WORD7 BANK 3 REGISTERS PROXIMITY_DETECTION_RATE REGISTER 0x003 FP_PROXIMITY_RECAL REGISTER 0x004 LP_PROXIMITY_RECAL REGISTER 0x004 COMPARATOR 1 WORD0 - WORD3 PROXIMITY PROXIMITY TIMING CONTROL LOGIC LP_PROXIMITY_CNT REGISTER 0x002
FF_SKIP_CNT
The proximity detection fast FIFO is used by the on-chip logic to determine if proximity is detected . The fast FIFO expects to receive samples from the converter at a set rate. FF_SKIP_CNT (Register 0x002[3:0]) is the fast filter skip control, which used to normalize the frequency of the samples going into the FIFO, regardless of how many conversion stages are in a sequence. This value determines which CDC samples are not used (skipped) in the proximity detection fast FIFO. Determining the FF_SKIP_CNT value is required only once during the initial setup of the capacitance sensor interface. Table 13 shows how FF_SKIP_CNT controls the update rate to the fast FIFO. Recommended value for this setting, when using all eight conversion stages on the AD7148, is FF_SKIP_CNT = 0000 = no samples skipped.
PROXIMITY 1
=WORD(N) N0
8 PROXIMITY SLOW_FILTER_EN SW1
7
STAGEx_FF_AVG BANK 3 REGISTERS COMPARATOR 2 AVERAGE - AMBIENT
PROXIMITY 2
STAGEx_FF_WORDx
PROXIMITY_RECAL_LVL REGISTER 0x003 COMPARATOR 3 WORD0 - CDC VALUE STAGEx_SF_WORD0 STAGEx_SF_WORD1 STAGEx_SF_WORD2 SLOW_FILTER_UPDATE_LVL REGISTER 0x003 STAGEx_SF_WORD3 STAGEx_SF_WORD4 STAGEx_SF_WORD5 STAGEx_SF_WORD6 STAGEx_SF_WORD7 STAGEx_SF_AMBIENT BANK 3 REGISTERS
CDC OUTPUT CODE
AMBIENT VALUE STAGEx_SF_WORDx SENSOR CONTACT TIME
Figure 30. Proximity Detection Logic
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BANK 3 REGISTERS NOTES 1. SLOW_FILTER_EN IS SET AND SW1 IS CLOSED WHEN |STAGEx_SF_WORD0-STAGEx_SF_WORD 1| EXCEEDS THE VALUE PROGRAMMED IN THE SLOW_FILTER_UPDATE_LVL BITS PROVIDING PROXIMITY IS NOT SET. 2. PROXIMITY 1 IS SET WHEN |STAGEx_FF_WORD0- STAGEx_FF_WORD3| EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_DETECTION_RATE BITS. 3. PROXIMITY 2 IS SET WHEN |AVERAGE-AMBIENT| EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_RECAL_LVL BITS. 4. DESCRIPTION OF COMPARATOR FUNCTIONS: COMPARATOR 1: USED TO DETECT WHEN A USER IS APPROACHING OR LEAVING A SENSOR. COMPARATOR 2: USED TO DETECT WHEN A USER IS HOVERING OVER A SENSOR OR APPROACHING A SENSOR VERY SLOWLY. ALSO USED TO DETECT IF THE SENSOR AMBIENT LEVEL HAS CHANGED AS A RESULT OF USER INTERACTION. FOR EXAMPLE, HUMIDITY OR DIRT LEFT BEHIND ON SENSOR. COMPARATOR 3: USED TO ENABLE THE SLOW FILTER UPDATE RATE. THE SLOW FILTER IS UPDATED WHENSLOW_FILTER_EN IS SET AND PROXIMITY IS NOT SET.
AD7148
Table 13. FF_SKIP_CNT Settings
FF_ SKIP_ CNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Fast FIFO Update Rate Decimation = 128 1.536 x (SEQUENCE_STAGE_NUM + 1) ms 3.072 x (SEQUENCE_STAGE_NUM + 1) ms 4.608 x (SEQUENCE_STAGE_NUM + 1) ms 6.144 x (SEQUENCE_STAGE_NUM + 1) ms 7.68 x (SEQUENCE_STAGE_NUM + 1) ms 9.216 x (SEQUENCE_STAGE_NUM + 1) ms 10.752 x (SEQUENCE_STAGE_NUM + 1) ms 12.288 x (SEQUENCE_STAGE_NUM + 1) ms 13.824 x (SEQUENCE_STAGE_NUM + 1) ms 15.36 x (SEQUENCE_STAGE_NUM + 1) ms 16.896 x (SEQUENCE_STAGE_NUM + 1) ms 18.432 x (SEQUENCE_STAGE_NUM + 1) ms 19.968 x (SEQUENCE_STAGE_NUM + 1) ms 21.504 x (SEQUENCE_STAGE_NUM + 1) ms 23.04 x (SEQUENCE_STAGE_NUM + 1) ms 24.576 x (SEQUENCE_STAGE_NUM + 1) ms
Decimation = 64 0.768 x (SEQUENCE_STAGE_NUM + 1) ms 1.536 x (SEQUENCE_STAGE_NUM + 1) ms 2.3 x (SEQUENCE_STAGE_NUM + 1) ms 3.072 x (SEQUENCE_STAGE_NUM + 1) ms 3.84 x (SEQUENCE_STAGE_NUM + 1) ms 4.6 x (SEQUENCE_STAGE_NUM + 1) ms 5.376 x (SEQUENCE_STAGE_NUM + 1) ms 6.144 x (SEQUENCE_STAGE_NUM + 1) ms 6.912x (SEQUENCE_STAGE_NUM + 1) ms 7.68 x (SEQUENCE_STAGE_NUM + 1) ms 8.448x (SEQUENCE_STAGE_NUM + 1) ms 9.216 x (SEQUENCE_STAGE_NUM + 1) ms 9.984 x (SEQUENCE_STAGE_NUM + 1) ms 10.752 x (SEQUENCE_STAGE_NUM + 1) ms 11.52 x (SEQUENCE_STAGE_NUM + 1) ms 12.288 x (SEQUENCE_STAGE_NUM + 1) ms
Decimation = 256 3.072 x (SEQUENCE_STAGE_NUM + 1) ms 6.144 x (SEQUENCE_STAGE_NUM + 1) ms 9.216 x (SEQUENCE_STAGE_NUM + 1) ms 12.288 x (SEQUENCE_STAGE_NUM + 1) ms 15.36 x (SEQUENCE_STAGE_NUM + 1) ms 18.432 x (SEQUENCE_STAGE_NUM + 1) ms 21.504 x (SEQUENCE_STAGE_NUM + 1) ms 24.576 x (SEQUENCE_STAGE_NUM + 1) ms 27.648 x (SEQUENCE_STAGE_NUM + 1) ms 30.72 x (SEQUENCE_STAGE_NUM + 1) ms 33.792 x (SEQUENCE_STAGE_NUM + 1) ms 36.864 x (SEQUENCE_STAGE_NUM + 1) ms 39.936 x (SEQUENCE_STAGE_NUM + 1) ms 43.008 x (SEQUENCE_STAGE_NUM + 1) ms 46.08 x (SEQUENCE_STAGE_NUM + 1) ms 49.152 x (SEQUENCE_STAGE_NUM + 1) ms
Rev. 0 | Page 21 of 56
AD7148 ENVIRONMENTAL CALIBRATION
The AD7148 provides on-chip capacitance sensor calibration to automatically adjust for environmental conditions that have an effect on the capacitance sensor ambient levels. Capacitance sensor output levels are sensitive to temperature, humidity, and in some cases, dirt. The AD7148 achieves optimal and reliable sensor performance by continuously monitoring the CDC ambient levels and correcting for any changes by adjusting the STAGEx_ HIGH_THRESHOLD and STAGEx_LOW_THRESHOLD register values, as described in Equation 1 and Equation 2. The CDC ambient level is defined as the capacitance sensor output level during periods when the user is not approaching or in contact with the sensor. The compensation logic runs automatically on every conversion after configuration when the AD7148 is not being touched, which allows the AD7148 to account for rapidly changing environmental conditions. The ambient compensation control registers give the host access to general setup and controls for the compensation algorithm. On-chip RAM stores the compensation data for each conversion stage, as well as setup information specific to each stage. Figure 31 shows an example of an ideal capacitance sensor behavior where the CDC ambient level remains constant, regardless of the environmental conditions. The CDC output shown is for a pair of differential button sensors, where one sensor caused an increase and the other caused a decrease in measured capacitance when activated. The positive and negative sensor threshold levels are calculated as a percentage of the STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW values based on the threshold sensitivity settings and the ambient value. These values are sufficient to detect a sensor contact, resulting in the AD7148 asserting the INT output when threshold levels are exceeded.
SENSOR 1 INT ASSERTED STAGEx_HIGH_THRESHOLD
CDC OUTPUT CODES
CAPACITANCE SENSOR BEHAVIOR WITHOUT CALIBRATION
Figure 32 shows the typical behavior of a capacitance sensor with no applied calibration. This figure shows ambient levels drifting over time as environmental conditions change. The ambient level drift results in the detection of a missed user contact on Sensor 2. This is a result of the initial low offset level remaining constant while the ambient levels drifted upward beyond the detection range.
SENSOR 1 INT ASSERTED STAGEx_HIGH_THRESHOLD
CDC OUTPUT CODES
CDC AMBIENT VALUE DRIFTING
STAGEx_LOW_THRESHOLD SENSOR 2 INT NOT ASSERTED
t
CHANGING ENVIRONMENTAL CONDITIONS
Figure 32. Typical Sensor Behavior Without Calibration Applied
The Capacitance Sensor Behavior with Calibration section describes how the AD7148 adaptive calibration algorithm prevents errors such as this from occurring.
CAPACITANCE SENSOR BEHAVIOR WITH CALIBRATION
The AD7148 on-chip adaptive calibration algorithm prevents sensor detection errors such as the one shown in Figure 32. Error prevention is accomplished by monitoring CDC ambient levels and readjusting the initial STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW values according to the amount of ambient drift measured on each sensor. The internal STAGEx_ HIGH_THRESHOLD and STAGEx_LOW_THRESHOLD values described in Equation 1 and Equation 2 are automatically updated based on the new values of STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW. This closed-loop routine ensures the reliability and repeatable operation of every sensor connected to the AD7148 under dynamic environmental conditions. Figure 33 shows a simplified example of how the AD7148 applies the adaptive calibration process resulting in no interrupt errors under changing CDC ambient levels due to environmental conditions.
CDC AMBIENT VALUE
STAGEx_LOW_THRESHOLD SENSOR 2 INT ASSERTED
t
CHANGING ENVIRONMENTAL CONDITIONS
Figure 31. Ideal Sensor Behavior with a Constant Ambient Level
Rev. 0 | Page 22 of 56
07155-030
07155-031
AD7148
SENSOR 1 INT ASSERTED 2 1
CDC OUTPUT CODES
3
STAGEx_HIGH_THRESHOLD (POSTCALIBRATED REGISTER VALUE)
Slow FIFO update rate in full power mode is equal to AVG_FP_SKIP x [(3 x Decimation Rate) x (SEQUENCE_STAGE_NUM +1) x (FF_SKIP_CNT +1) x 4x10-7] Slow FIFO update rate in low power mode is equal to (AVG_LP_SKIP +1) x [(3 x Decimation Rate) x (SEQUENCE_STAGE_NUM +1) x (FF_SKIP_CNT +1) x 4x10-7]/[(FF_SKIP_CNT +1 ) + LP_CONV_DELAY] The slow FIFO is used by the on-chip logic to track the ambient capacitance value. The slow FIFO expects to receive samples from the converter at a rate of 25 ms. AVG_FP_SKIP and AVG_LP_ SKIP are used to normalize the frequency of the samples going into the FIFO, regardless of how many conversion stages are in a sequence. Determining the AVG_FP_SKIP and AVG_LP_SKIP values is required only once during the initial setup of the capacitance sensor interface. When using all eight conversion stages, recommended values for these settings are AVG_FP_SKIP = 00 = skip 3 samples AVG_LP_SKIP = 00 = skip 0 samples
CDC AMBIENT VALUE DRIFTING 6 5 4 SENSOR 2 INT ASSERTED CHANGING ENVIRONMENTAL CONDITIONS STAGEx_LOW_THRESHOLD (POSTCALIBRATED REGISTER VALUE)
t
Figure 33. Typical Sensor Behavior with Calibration Applied on the Data Path
SLOW FIFO
As shown in Figure 30, there are a number of FIFOs implemented on the AD7148. These FIFOs are located in Bank 3 of the on-chip memory. The slow FIFOs are used by on-chip logic to monitor the ambient capacitance level from each sensor.
07155-032
NOTES 1. INITIAL STAGEx_OFFSET_HIGH REGISTER VALUE. 2. POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD. 3. POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD. 4. INITIAL STAGEx_LOW_THRESHOLD. 5. POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD. 6. POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD.
SLOW_FILTER_UPDATE_LVL
The SLOW_FILTER_UPDATE_LVL (Address 0x003[15:14]) controls whether the most recent CDC measurement goes into the slow FIFO (slow filter) or not. The slow filter is updated when the difference between the current CDC value and last value pushed into the slow FIFO is greater than SLOW_FILTER_ UPDATE_LVL.
AVG_FP_SKIP and AVG_LP_SKIP
In Register 0x001, Bits[13:12]are the slow FIFO skip control for full power mode, AVG_FP_SKIP. Bits[15:14] in the same register are the slow FIFO skip control for low power mode, AVG_LP_SKIP. These values determine which CDC samples are not used (skipped) in the slow FIFO. Changing theses values slows down or speeds up the rate at which the ambient capacitance value tracks the measured capacitance value read by the converter.
Equations for On-Chip Logic Stage High and Logic Stage Low Threshold Calculation
STAGEx _ OFFSET _ HIGH STAGEx_HIGH_THRESHOLD = STAGE_SF_AMBIENT + + 4 STAGEx_ OFFSET _ HIGH STAGEx_ OFFSET_ HIGH - 4 x POS_THRESHOLD_SENSITIVITY 16 STAGEx _ OFFSET _ LOW STAGEx_LOW_THRESHOLD = STAGE_SF_AMBIENT + + 4 STAGEx _ OFFSET _ LOW STAGEx _ OFFSET_ LOW - 4 x POS_THRESHOLD_SENSITIVITY 16
(1)
(2)
Rev. 0 | Page 23 of 56
AD7148 ADAPTIVE THRESHOLD AND SENSITIVITY
The AD7148 provides an on-chip self-learning adaptive threshold and sensitivity algorithm. This algorithm continuously monitors the output levels of each sensor and automatically rescales the threshold levels proportionally to the sensor area covered by the user. As a result, the AD7148 maintains optimal threshold and sensitivity levels for all types of users, regardless of finger size. The threshold level is always referenced from the ambient level and is defined as the CDC converter output level that must be exceeded for a valid sensor contact. The sensitivity level is defined as how sensitive the sensor is before a valid contact is registered. Figure 34 provides an example of how the adaptive threshold and sensitivity algorithm works. The positive and negative sensor threshold levels are calculated as a percentage of the STAGEx_ OFFSET_HIGH and STAGEx_OFFSET_LOW values, based on the threshold sensitivity settings and the ambient value. On configuration, initial estimates are supplied for both STAGEx_ OFFSET_HIGH and STAGEx_OFFSET_LOW, after which the calibration engine automatically adjusts the STAGEx_HIGH_ THRESHOLD and STAGEx_LOW_THRESHOLD values for sensor response. The AD7148 tracks the average maximum and minimum values measured from each sensor. These values give an indication of how the user is interacting with the sensor. A large finger gives a large average maximum or minimum value, and a small finger gives smaller values. When the average maximum or minimum value changes, the threshold levels are rescaled to ensure that the threshold levels are appropriate for the current user. Figure 35 shows how the minimum and maximum sensor responses are tracked by the on-chip logic. Reference A in Figure 34 shows an undersensitive threshold level for a small finger user, demonstrating the disadvantages of a fixed threshold level. By enabling the adaptive threshold and sensitivity algorithm, the positive and negative threshold levels are determined by the POS_THRESHOLD_SENSITIVITY and NEG_THRESHOLD_ SENSITIVITY values and the most recent average maximum sensor output value. These bits can be used to select 16 different positive and negative sensitivity levels ranging between 25% and 95.32% of the most recent average maximum output level referenced from the ambient value. The smaller the sensitivity percentage setting, the easier it is to trigger a sensor activation. Reference B shows that the positive adaptive threshold level is set at almost mid-sensitivity with a 62.51% threshold level by setting POS_THRESHOLD_SENSITIVITY = 1000. Figure 34 also provides a similar example for the negative threshold level with NEG_THRESHOLD_SENSITIVITY = 0011.
AVERAGE MAX VALUE 95.32% STAGEx_OFFSET_HIGH IS UPDATED AVERAGE MAX VALUE STAGEx_OFFSET_HIGH 95.32% STAGEx_OFFSET_HIGH IS UPDATED HERE 62.51% = POS ADAPTIVE THRESHOLD LEVEL 25% AMBIENT LEVEL 25% NEG ADAPTIVE THRESHOLD LEVEL = 39.08% STAGEx_OFFSET_LOW 95.32% STAGEx_OFFSET_LOW IS UPDATED HERE 25%
B A
CDC OUTPUT CODES
62.51% = POS ADAPTIVE THRESHOLD LEVEL
25%
NEG ADAPTIVE THRESHOLD LEVEL = 39.08%
STAGEx_OFFSET_LOW IS UPDATED HERE 95.32% SENSOR CONTACTED BY SMALL FINGER SENSOR CONTACTED BY LARGE FINGER
07155-033
Figure 34. Threshold Sensitivity Example with POS_THRESHOLD_SENSITIVITY = 1000 and NEG_THRESHOLD_SENSITIVITY = 0011
Rev. 0 | Page 24 of 56
AD7148
STAGEx_MAX_WORD0 STAGEx_MAX_WORD1 STAGEx_MAX_WORD2 STAGEx_MAX_WORD3 - 16-BIT CDC 16 MAX LEVEL DETECTION LOGIC STAGEx_MAX_AVG BANK 3 REGISTERS STAGEx_MAX_TEMP BANK 3 REGISTERS STAGEx_HIGH_THRESHOLD BANK 3 REGISTERS STAGEx_MIN_WORD0 STAGEx_MIN_WORD1 STAGEx_MIN_WORD2 STAGEx_MIN_WORD3 MIN LEVEL DETECTION LOGIC STAGEx_MIN_AVG BANK 3 REGISTER3 STAGEx_MIN_TEMP BANK 3 REGISTERS STAGEx_LOW_THRESHOLD BANK 3 REGISTERS
07155-034
BANK 3 REGISTERS
BANK 3 REGISTERS
Figure 35. Tracking the Minimum and Maximum Average Sensor Values
Table 14. Additional Information About Environmental Calibration and Adaptive Threshold Registers
Bit NEG_THRESHOLD_SENSITIVITY NEG_PEAK_DETECT Register Location Bank 2 Bank 2 Description Used in Equation 2. This value is programmed once at startup. Used by internal adaptive threshold logic only. The NEG_PEAK_DETECT is set to a percentage of the difference between the ambient CDC value and the minimum average CDC value. If the output of the CDC gets within the NEG_PEAK_DETECT percentage of the minimum average, only then is the minimum average value updated. Used in Equation 1. This value is programmed once at startup. Used by internal adaptive threshold logic only. The POS_PEAK_DETECT is set to a percentage of the difference between the ambient CDC value and the maximum average CDC value. If the output of the CDC gets within the POS_PEAK_DETECT percentage of the maximum average, only then is the maximum average value updated. Used in Equation 2. An initial value (based on sensor characterization) is programmed into this register at startup. The AD7148 on-chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. Set to 80% of the STAGEx_OFFSET_LOW_CLAMP value. Used in Equation 1. An initial value (based on sensor characterization) is programmed into this register at startup. The AD7148 on-chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. Set to 80% of the STAGEx_OFFSET_HIGH_CLAMP value. Used by internal environmental calibration and adaptive threshold algorithms only. An initial value (based on sensor characterization) is programmed into this register at startup. The value in this register prevents a user from causing sensor output value to exceed the expected nominal value. Set to the maximum expected sensor response, maximum change in CDC output code. Used by internal environmental calibration and adaptive threshold algorithms only. An initial value (based on sensor characterization) is programmed into this register at startup. The value in this register prevents a user from causing sensor output value to exceed the expected nominal value. Set to the minimum expected sensor response, minimum change in CDC output code . Used in Equation 1 and Equation 2. This is the ambient sensor output, when the sensor is not touched, as calculated using the slow FIFO. Equation 1 value. Equation 2 value.
POS_THRESHOLD_SENSITIVITY POS_PEAK_DETECT
Bank 2 Bank 2
STAGEx_OFFSET_LOW
Bank 2
STAGEx_OFFSET_HIGH
Bank 2
STAGEx_OFFSET_HIGH_CLAMP
Bank 2
STAGEx_OFFSET_LOW_CLAMP
Bank 2
STAGEx_SF_AMBIENT STAGEx_HIGH_THRESHOLD STAGEx_LOW_THRESHOLD
Bank 3 Bank 3 Bank 3
Rev. 0 | Page 25 of 56
AD7148 INTERRUPT OUTPUT
The AD7148 has an interrupt output that triggers an interrupt service routine on the host processor. The INT signal is on Pin 12 and is an open-drain output. There are two types of interrupt events on the AD7148: a CDC conversion complete interrupt and a sensor threshold interrupt. Each interrupt has enable and status registers. The conversion complete and sensor threshold interrupts can be enabled on a per conversion stage basis. The status registers indicate what type of interrupt triggered the INT pin. Status registers are cleared, and the INT signal is reset high during a read operation. The signal returns high as soon as the read address is set up.
SENSOR TOUCH INTERRUPT
The sensor touch interrupt mode is implemented when the host processor requires an interrupt only when a sensor is contacted. Configuring the AD7148 into this mode results in the interrupt being asserted when the user makes contact with the sensor and again when the user lifts off the sensor. The second interrupt is required to alert the host processor that the user is no longer contacting the sensor. The registers located at Address 0x005 (STAGEx_LOW_INT_EN) and Address 0x006 (STAGEx_HIGH_INT_EN) are used to enable the interrupt output for each stage. The registers located at Address 0x008 (STAGEx_LOW_LIMIT_INT) and Address 0x009 (STAGEx_HIGH_LIMIT_INT) are used to read back the interrupt status for each stage. Figure 36 shows the interrupt output timing during contact with one of the sensors connected to STAGE0 while operating in the sensor touch interrupt mode. For a low limit configuration, the interrupt output is asserted as soon as the sensor is contacted and again after the user has stopped contacting the sensor. Note that the interrupt output remains low until the host processor reads back the interrupt status registers located at Address 0x008 and Address 0x009. The interrupt output is asserted when there is a change in the threshold status bits. This change indicates that a user is now touching the sensor(s) for the first time, the number of sensors being touched has changed, or the user is no longer touching the sensor(s). Reading the status bits in the interrupt status register shows the current sensor activations.
CONVERSION STAGE STAGE0 STAGE1
CDC CONVERSION-COMPLETE INTERRUPT
The AD7148 interrupt signal asserts low to indicate the completion of a conversion stage, and new conversion result data is available in the registers. The interrupt can be independently enabled for each conversion stage. Each conversion-stage-complete interrupt can be enabled via the STAGEx_COMPLETE_INT_EN register (Address 0x007). This register has a bit that corresponds to each conversion stage. Setting this bit to 1 enables the interrupt for that stage. Clearing this bit to 0 disables the conversion complete interrupt for that stage. In normal operation, the interrupt is enabled only for the last stage in a conversion sequence. For example, if there are five conversion stages, the conversion-complete interrupt for STAGE4 is enabled. INT asserts only when all five conversion stages are complete, and the host can read new data from all five results registers. The interrupt is cleared by reading the STAGEx_COMPLETE_INT_ STATUS register located at Address 0x00A. Register 0x00A is the conversion-complete interrupt status register. Each bit in this register corresponds to a conversion stage. If a bit is set, it means that the conversion-complete interrupt for the corresponding stage has been triggered. This register is cleared on a read, provided that the underlying condition that triggered the interrupt has gone away.
2 SERIAL READBACK
4
INT OUTPUT NOTES: 1. USER TOUCHING DOWN ON SENSOR 2. ADDRESS 0x008 READ BACK TO CLEAR INTERRUPT 3. USER LIFTING OFF OF SENSOR 4. ADDRESS 0x008 READ BACK TO CLEAR INTERRUPT
Figure 36. Example of Sensor Touch Interrupt
Rev. 0 | Page 26 of 56
07155-035
AD7148 ACSHIELD OUTPUT
The AD7148 measures capacitance between CINx and ground. Any capacitance to ground on the signal path between the CINx pins and the sensor is included in the conversion result. To eliminate the stray capacitance to ground, the ACSHIELD signal should be used to shield the connection between the sensor and CINx, as shown in Figure 37. The plane around the sensors should also be connected to ACSHIELD. The ACSHIELD output is the same signal waveform as the excitation signal on CINx. Therefore, there is no ac current between CINx and ACSHIELD, and any capacitance between these pins does not affect the CINx charge transfer. Using ACSHIELD eliminates capacitance-to-ground pick-up, which means that the AD7148 can be placed up to 60 cm away from the sensors. This allows the AD7148 to be placed on a separate PCB from the sensors, provided that the connections between the sensors and the CINx inputs are correctly shielded, using ACSHIELD.
SENSOR PCB
CIN0 CIN1 AD7148 CIN2 CIN3 AC SHIELD
Figure 37. ACSHIELD
Rev. 0 | Page 27 of 56
07155-036
AD7148 I2C-COMPATIBLE SERIAL INTERFACE
The AD7148 supports the industry standard 2-wire I2C serial interface protocol. The two wires associated with the I2C timing are the SCLK and the SDA inputs. The SDA is an I/O pin that allows both register write and register readback operations. The AD7148 is always a slave device on the I2C serial interface bus. It has a single fixed 7-bit device address, Address 0101 110. The AD7148 responds when the master device sends its device address over the bus. The AD7148 cannot initiate data transfers on the bus.
Table 15. AD7148 I C Device Address
DEV A6 0 DEV A5 1 DEV A4 1 DEV A3 0 DEV A2 1 DEV A1 1 DEV A0 0
2
are don't care bits. The address is contained in the 10 LSBs of the register address bytes.
MSB 7 X 6 X 5 X 4 X 3 X 2 X 1 Register Address Bit 9 LSB 0 Register Address Bit 8
The following bit map shows the lower register address bytes.
MSB 7 Reg Add Bit 7 LSB 6 Reg Add Bit 6 5 Reg Add Bit 5 4 Reg Add Bit 4 3 Reg Add Bit 3 2 Reg Add Bit 2 1 Reg Add Bit 1 0 Reg Add Bit 0
Data Transfer
Data is transferred over the I2C serial interface in 8-bit bytes. The master initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line, SDA, while the serial clock line, SCLK, remains high. This indicates that an address/data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit that determines the direction of the data transfer. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as the acknowledge bit. All other devices on the bus now remain idle while the selected device waits for data to be read from, or written to it. If the R/W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device. Data is sent over the serial bus in a sequence of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to-high transition when the clock is high can be interpreted as a stop signal. The number of data bytes transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. When all data bytes are read or written, a stop condition is established. A stop condition is defined by a low-to-high transition on SDA, while SCLK remains high. If the AD7148 encounters a stop condition, it returns to its idle condition, and the address pointer register resets to Address 0x00. The third data byte contains the eight MSBs of the data to be written to the internal register. The fourth data byte contains the eight LSBs of data to be written to the internal register. The AD7148 address pointer register automatically increments after each write, allowing the master to sequentially write to all registers on the AD7148-1 in the same write transaction. However, the address pointer register does not wrap around after the last address. Any data written to the AD7148 after the address pointer has reached its maximum value is discarded. All registers on the AD7148 have 16 bits. Two consecutive 8-bit data bytes are combined and written to the 16-bit registers. To avoid errors, all writes to the device must contain an even number of data bytes. To finish the transaction, the master generates a stop condition on SDO or generates a repeat start condition if the master is to maintain control of the bus.
Reading Data over the I2C Bus
To read from the AD7148, the address pointer register must first be set to the address of the required internal register. The master performs a write transaction and writes to the AD7148 to set the address pointer. The master then outputs a repeat start condition to keep control of the bus or, if this is not possible, ends the write transaction with a stop condition. A read transaction is initiated, with the R/W bit set to 1. The AD7148 supplies the upper eight bits of data from the addressed register in the first readback byte, followed by the lower eight bits in the next byte. This operation is shown in Figure 39 and Figure 40. Because the address pointer automatically increases after each read, the AD7148 continues to output readback data until the master puts a no acknowledge and a stop condition on the bus. If the address pointer reaches its maximum value, and the master continues to read from the part, the AD7148 repeatedly sends data from the last register addressed.
Writing Data over the I2C Bus
The process for writing to the AD7148 over the I2C bus is shown in Figure 38 and Figure 40. The device address is sent over the bus followed by the R/W bit set to 0. This is followed by two bytes of data that contain the 10-bit address of the internal data register to be written. The following bit map shows the upper register address bytes. Note that Bit 7 to Bit 2 in the upper address byte
Rev. 0 | Page 28 of 56
AD7148
START AD7148 DEVICE ADDRESS SDA DEV A6 DEV A5 DEV A4 DEV A3 DEV DEV A2 A1 DEV A0 R/W ACK REGISTER ADDRESS[A15:A8] A15 A14 A9 A8 ACK A7 REGISTER ADDRESS[A7:A0] A6 A1 A0
t1
SCLK 1 2 3 4 5 6
t3
7 8 9 10 11 16 17 18 19 20 25 26
t2
STOP REGISTER DATA[D15:D8] ACK D15 D14 D9 D8 ACK D7 REGISTER DATA[D7:D0] D6 D1 D0 ACK START
t8
AD7148 DEVICE ADDRESS DEV A6 DEV A5 DEV A4
t4
27 28 29 34 35 36 37
t5
38 43 44 45
t6
46
t7
1 2 3
Figure 38. Example of I2C Timing for Single Register Write Operation
START AD7148-1 DEVICE ADDRESS SDA DEV A6 DEV A5 DEV A4 DEV A3 DEV DEV A2 A1 DEV A0 R/W ACK REGISTER ADDRESS[A15:A8] A15 A14 A9 A8 ACK A7 REGISTER ADDRESS[A7:A0] A6 A1 A0 ACK
t1
SCLK 1 2 3 4 5 6
t3
7 8 9 10 11 16 17 18 19 20 25 26 27
t2
P SR DEV A6 USING REPEATED START 28 29 30 34 AD7148-1 DEVICE ADDRESS DEV A5 DEV A1 DEV A0 R/W ACK D7 REGISTER DATA[D7:D0] D6 D1 D0 ACK
t8
AD7148 DEVICE ADDRESS DEV A6 DEV A5 DEV A4
t4
35 36 37 38
t5
39 44 45 46
t6
t7
1 2 3
P
S DEV A6
AD7142-1 DEVICE ADDRESS DEV A5 DEV A1 DEV A0 R/W ACK D7
REGISTER DATA[D7:D0] D6 D1 D0 ACK
P
SEPARATE READ AND WRITE TRANSACTIONS 28 29 30 34
t4
35 36 37 38
t5
39 44 45 46
Figure 39. Example of I2C Timing for Single Register Readback Operation
Rev. 0 | Page 29 of 56
07155-038
NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA. 4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE TWO LSB X's ARE DON'T CARE BITS. 5. 16-BIT REGISTER ADDRESS[A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE THE UPPER LSB X's ARE DON'T CARE BITS. 6. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. 7. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. 8. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION.
07155-037
NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE X ARE DON'T CARE BITS. 4. 16-BIT REGISTER ADDRESS[A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE X ARE DON'T CARE BITS. 5. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. 6. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
AD7148
WRITE S 6-BIT DEVICE W ADDRESS REGISTER ADDR [15:8] REGISTER ADDR [7:0] WRITE DATA HIGH BYTE [15:8] WRITE DATA LOW BYTE [7:0] WRITE DATA HIGH BYTE [15:8] WRITE DATA LOW BYTE [7:0]
ACK
ACK
ACK
ACK
ACK
ACK
P
READ (USING REPEATED START) S 6-BIT DEVICE W ADDRESS REGISTER ADDR HIGH BYTE REGISTER ADDR LOW BYTE 6-BIT DEVICE ADDRESS READ DATA HIGH BYTE [15:8] READ DATA LOW BYTE [7:0] READ DATA HIGH BYTE [15:8] READ DATA LOW BYTE [7:0]
ACK
ACK
ACK SR
R ACK
ACK
ACK
ACK P
READ (WRITE TRANSACTION SETS UP REGISTER ADDRESS) S 6-BIT DEVICE W ADDRESS REGISTER ADDR HIGH BYTE REGISTER ADDR LOW BYTE P S 6-BIT DEVICE ADDRESS READ DATA HIGH BYTE [15:8] READ DATA LOW BYTE [7:0] READ DATA HIGH BYTE [15:8] READ DATA LOW BYTE [7:0]
ACK
ACK
ACK
R ACK
ACK
ACK
ACK P
07155-039
OUTPUT FROM MASTER OUTPUT FROM AD7142
S = START BIT P = STOP BIT SR = REPEATED START BIT
ACK = ACKNOWLEDGE BIT ACK = NO ACKNOWLEDGE BIT
Figure 40. Example of Sequential I2C Write and Readback Operation
VDRIVE INPUT
The supply voltage to all pins associated with the I C serial interface (SCLK, SDA) is separate from the main VCC supplies and is connected to the VDRIVE pin.
2
This arrangement allows the AD7148 to be connected directly to processors whose supply voltage is less than the minimum operating voltage of the AD7148 without the need for external level-shifters. The VDRIVE pin can be connected to voltage supplies as low as 1.65 V and as high as VCC.
Rev. 0 | Page 30 of 56
AD7148 PCB DESIGN GUIDELINES
CAPACITIVE SENSOR BOARD MECHANICAL SPECIFICATIONS
Table 16.
Parameter Distance from Edge of Any Sensor to Edge of Grounded Metal Object Distance Between Sensor Edges 1 Distance Between Bottom of Sensor Board and Controller Board or Grounded Metal Casing 2
1
Symbol D1 D2 = D3 = D4 D5
Min 0.1 0
Typ
Max
1.0
Unit mm mm mm
The distance is dependent on the application and the positioning of the switches relative to each other and with respect to the user's finger positioning and handling. Adjacent sensors, with 0 minimum space between them, are implemented differentially. 2 The 1.0 mm specification is meant to prevent direct sensor board contact with any conductive material. This specification does not guarantee no EMI coupling from the controller board to the sensors. Address potential EMI coupling issues by placing a grounded metal shield between the capacitive sensor board and the main controller board, as shown in Figure 43.
CAPACITIVE SENSOR BOARD D5 GROUNDED METAL SHIELD
METAL OBJECT
CAPACITIVE SENSOR PRINTED CIRCUIT
CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING
Figure 43. Capacitive Sensor Board with Grounded Shield
D4 SLIDER
CHIP SCALE PACKAGES
The lands on the chip scale package (CP-16-13) are rectangular. The printed circuit board pad for this package should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. Center the land on the pad to maximize the solder joint size. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. To avoid shorting, provide a clearance of at least 0.25 mm between the thermal pad and the inner edges of the land pattern on the printed circuit board. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. Connect the printed circuit board thermal pad to GND.
BUTTONS
D3
D2
D1
07155-040
Figure 41. Capacitive Sensor Board Mechanicals Top View
CAPACITIVE SENSOR BOARD D5 CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING
07155-041
Figure 42. Capacitive Sensor Board Mechanicals Side View
Rev. 0 | Page 31 of 56
07155-042
8-WAY SWITCH
AD7148 POWER-UP SEQUENCE
When the AD7148 is powered up, the following sequence is recommended when initially developing the AD7148 and host microprocessor serial interface: 1. 2. Turn on the power supplies to the AD7148. Write to the Bank 2 registers at Address 0x080 through Address 0x0BF. These registers are contiguous, so a sequential register write sequence can be applied. Note that the Bank 2 register values are unique for each application. Register values come from characterization of the sensor in the application and may be provided by Analog Devices after the sensor board has been developed. Write to the Bank 1 registers at Address 0x000 through Address 0x007, as outlined in the following list. Address 0x003 = 0x0419 Address 0x004 = 0x0832 Address 0x005 = interrupt enable register; depends on required interrupt behavior Address 0x006 = interrupt enable register; depends on required interrupt behavior Address 0x007 = interrupt enable register; depends on required interrupt behavior Write to the Bank 1 register, Address 0x001 = 0x00FF; depends on number of conversion stages used. Read back the corresponding interrupt status register at Address 0x008, Address 0x009, or Address 0x00A. The address to be read back is determined by the interrupt output configuration, as explained in the Interrupt Output section. Note that the specific registers required to be read back depend on each application. For buttons, the interrupt status registers are read back, while other sensors read data back according to the requirements of the slider or wheel algorithm. Analog Devices provides this information after the sensor board has been developed. Repeat Step 5 every time INT is asserted.
4. 5.
3.
Caution
At this time, Address 0x001 must remain set to Default Value 0x0000 during this contiguous write operation.
Register values: Address 0x000 = 0x0B2 Address 0x001 = 0x000 Address 0x002 = 0x3230 (depends on number of conversion stages used)
POWER SUPPLY 1
6.
7.
2 HOST SERIAL INTERFACE
3
4
5
6
6
CONVERSION STAGE
CONVERSION STAGES DISABLED
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
9
10
11
0
1
2
9
10
11
0
1
FIRST CONVERSION SEQUENCE
SECOND CONVERSION SEQUENCE
THIRD CONVERSION SEQUENCE
Figure 44. Recommended Start-Up Sequence
Rev. 0 | Page 32 of 56
07155-043
AD7148 INTERRUPT
AD7148 TYPICAL APPLICATION CIRCUIT
VDRIVE VDRIVE 2.2k 2.2k 2.2k INT
12 11 10 9
VDRIVE
16
15
14
13
CIN3
CIN2
CIN1
CONNECT PLANE AROUND SENSORS TO ACSHIELD
BUTTON
1 2
CIN4 CIN5 CIN6
CIN0
HOST WITH I2C INTERFACE INT SCK SDO
BUTTON
3 4
AD7148
ACSHIELD
SCLK SDA
SLIDER
BIAS
7
5
6
10nF 0.1F
8
VCC
BUTTON
GND
CIN7
VDRIVE
VCC 2.7V TO 3.6V 1F TO 10F (OPTIONAL)
07155-044
Figure 45. Typical Application Circuit
Rev. 0 | Page 33 of 56
AD7148 REGISTER MAP
The AD7148 address space is divided into three different register banks, referred to as Register Bank 1, Register Bank 2, and Register Bank 3. Figure 46 illustrates the division of these three banks. Bank 1 registers contain control registers, CDC conversion control registers, interrupt enable registers, interrupt status registers, CDC 16-bit conversion data registers, device ID registers, and proximity status registers. Bank 2 registers contain the configuration registers used for uniquely configuring the CINx inputs for each conversion stage. Initialize the Bank 2 configuration registers immediately after power-up to obtain valid CDC conversion result data.
REGISTER BANK 1 ADDR 0x000 ADDR 0x001 SETUP CONTROL (1 REGISTER) CALIBRATION AND SETUP (4 REGISTERS) ADDR 0x080 ADDR 0x088 ADDR 0x090
Bank 3 registers contain the results of each conversion stage. These registers automatically update at the end of each conversion sequence. Although these registers are primarily used by the AD7148 internal data processing, they are accessible by the host processor for additional external data processing, if desired. Default values are undefined for Bank 2 registers and Bank 3 registers until after power-up and configuration of the Bank 2 registers.
REGISTER BANK 2 STAGE0 CONFIGURATION (8 REGISTERS) STAGE1 CONFIGURATION (8 REGISTERS) ADDR 0x0E0 ADDR 0x104 ADDR 0x128
REGISTER BANK 3 STAGE0 RESULTS (36 REGISTERS) STAGE1 RESULTS (36 REGISTERS) STAGE2 RESULTS (36 REGISTERS) STAGE3 RESULTS (36 REGISTERS) STAGE4 RESULTS (36 REGISTERS) STAGE5 RESULTS (36 REGISTERS) STAGE6 RESULTS (36 REGISTERS) STAGE7 RESULTS (36 REGISTERS)
64 REGISTERS
ADDR 0x005 INTERRUPT ENABLE (3 REGISTERS) ADDR 0x008 INTERRUPT STATUS (3 REGISTERS) ADDR 0x00B CDC 16-BIT CONVERSION DATA (8 REGISTERS) ADDR 0x013 UNUSED (4 REGISTERS) ADDR 0x017 DEVICE ID REGISTER ADDR 0x018 ADDR 0x042 PROXIMITY STATUS REGISTER ADDR 0x043 INVALID DO NOT ACCESS ADDR 0x7F0 INVALID DO NOT ACCESS
288 REGISTERS
ADDR 0x098 ADDR 0x0A0 ADDR 0x0A8 ADDR 0x0B0 ADDR 0x0B8
STAGE2 CONFIGURATION (8 REGISTERS) STAGE3 CONFIGURATION (8 REGISTERS) STAGE4 CONFIGURATION (8 REGISTERS) STAGE5 CONFIGURATION (8 REGISTERS) STAGE6 CONFIGURATION (8 REGISTERS) STAGE7 CONFIGURATION (8 REGISTERS)
ADDR 0x14C ADDR 0x170 ADDR 0x194 ADDR 0x1B8 ADDR 0x1DC
24 REGISTERS
Figure 46. Layout of Bank 1 Registers, Bank 2 Registers, and Bank 3 Registers
Rev. 0 | Page 34 of 56
07155-045
AD7148 DETAILED REGISTER DESCRIPTIONS
BANK 1 REGISTERS
All addresses and default values are expressed in hexadecimal format.
Table 17. PWR_CONTROL Register
Address 0x000 Data Bit [1:0] Default Value 0 Type R/W Mnemonic POWER_MODE Description Operating modes 00 = full power mode (normal operation, CDC conversions approximately every 36 ms) 01 = full shutdown mode (no CDC conversions) 10 = low power mode (automatic wake up operation) 11 = full shutdown mode (no CDC conversions) Low power mode conversion delay 00 = 200 ms 01 = 400 ms 10 = 600 ms 11 = 800 ms Number of stages in sequence (N + 1) 0000 = 1 conversion stage in sequence 0001 = 2 conversion stages in sequence ... Maximum value = 1011 = 12 conversion stages per sequence ADC decimation factor 00 = decimate by 256 01 = decimate by 128 10 = decimate by 64 11 = decimate by 64 Software reset control (self-clearing) 1 = resets all registers to default values Interrupt polarity control 0 = active low 1 = active high Excitation source control 0 = enable excitation source to CINx pins 1 = disable excitation source to CINx pins Set to 0 CDC bias current control 00 = normal operation 01 = normal operation + 20% 10 = normal operation + 35% 11 = normal operation + 50%
[3:2]
0
R/W
LP_CONV_DELAY
[7:4]
0
R/W
SEQUENCE_STAGE_NUM
[9:8]
0
R/W
DECIMATION
[10] [11]
0 0
R/W R/W
SW_RESET INT_POL
[12]
0
R/W
[13] [15:14]
0 0
R/W
Unused CDC_BIAS
Rev. 0 | Page 35 of 56
AD7148
Table 18. STAGEx_CAL_EN Register
Address 0x001 Data Bit [0] Default Value 0 Type R/W Mnemonic STAGE0_CAL_EN Description STAGE0 calibration enable 0 = disable 1 = enable STAGE1 calibration enable 0 = disable 1 = enable STAGE2 calibration enable 0 = disable 1 = enable STAGE3 calibration enable 0 = disable 1 = enable STAGE4 calibration enable 0 = disable 1 = enable STAGE5 calibration enable 0 = disable 1 = enable STAGE6 calibration enable 0 = disable 1 = enable STAGE7 calibration enable 0 = disable 1 = enable Set unused register bits to 0 Full power mode skip control 00 = skip 3 samples 01 = skip 7 samples 10 = skip 15 samples 11 = skip 31 samples Low power mode skip control 00 = use all samples 01 = skip 1 sample 10 = skip 2 samples 11 = skip 3 samples
[1]
0
R/W
STAGE1_CAL_EN
[2]
0
R/W
STAGE2_CAL_EN
[3]
0
R/W
STAGE3_CAL_EN
[4]
0
R/W
STAGE4_CAL_EN
[5]
0
R/W
STAGE5_CAL_EN
[6]
0
R/W
STAGE6_CAL_EN
[7]
0
R/W
STAGE7_CAL_EN
[11:8] [13:12]
0 0
R/W R/W
Unused AVG_FP_SKIP
[15:14]
0
R/W
AVG_LP_SKIP
Rev. 0 | Page 36 of 56
AD7148
Table 19. AMB_COMP_CTRL0 Register
Address 0x002 Data Bit [3:0] Default Value 0 Type R/W Mnemonic FF_SKIP_CNT Description Fast filter skip control (N+1) 0000 = no sequence of results is skipped 0001 = one sequence of results is skipped for every one allowed into fast FIFO 0010 = two sequences of results are skipped for every one allowed into fast FIFO 1011 = maximum value = 8 sequences of results are skipped for every one allowed into fast FIFO Calibration disable period in full power mode = FP_PROXIMITY_CNT x 16 x time taken for one conversion sequence in full power mode Calibration disable period in low power mode = LP_PROXIMITY_CNT x 4 x time taken for one conversion sequence in low power mode Full power to low power mode time out control 00 = 1.25 x (FP_PROXIMITY_CNT) 01 = 1.50 x (FP_PROXIMITY_CNT) 10 = 1.75 x (FP_PROXIMITY_CNT) 11 = 2.00 x (FP_PROXIMITY_CNT) Forced calibration control 0 = normal operation 1 = forces all conversion stages to recalibrate Conversion reset control (self-clearing) 0 = normal operation 1 = resets the conversion sequence back to STAGE0.
[7:4]
F
R/W
FP_PROXIMITY_CNT
[11:8]
F
R/W
LP_PROXIMITY_CNT
[13:12]
0
R/W
PWR_DOWN_TIMEOUT
[14]
0
R/W
FORCED_CAL
[15]
0
R/W
CONV_RESET
Table 20. AMB_COMP_CTRL1 Register
Address 0x003 Data Bit [7:0] [13:8] [15:14] Default Value 64 1 0 Type R/W R/W R/W Mnemonic PROXIMITY_RECAL_LVL PROXIMITY_DETECTION_RATE SLOW_FILTER_UPDATE_LVL Description Proximity recalibration level; value is multiplied by 16 to get actual recalibration level Proximity detection rate; value is multiplied by 16 to get actual detection rate Slow filter update level
Table 21. AMB_COMP_CTRL2 Register
Address 0x004 Data Bit [9:0] [15:10] Default Value 3FF 3F Type R/W R/W Mnemonic FP_PROXIMITY_RECAL LP_PROXIMITY_RECAL Description Full power mode proximity recalibration time control Low power mode proximity recalibration time control
Rev. 0 | Page 37 of 56
AD7148
Table 22. STAGEx_LOW_INT_EN Register
Address 0x005 Data Bit [0] Default Value 0 Type R/W Mnemonic STAGE0_LOW_INT_EN Description STAGE0 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded STAGE1 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE1 low threshold is exceeded STAGE2 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE2 low threshold is exceeded STAGE3 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE3 low threshold is exceeded STAGE4 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE4 low threshold is exceeded STAGE5 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE5 low threshold is exceeded STAGE6 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE6 low threshold is exceeded STAGE7 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE7 low threshold is exceeded Set unused register bits to 0 GPIO setup 00 = disable GPIO pin 01 = configure GPIO as an input 10 = configure GPIO as an active low output 11 = configure GPIO as an active high output GPIO input configuration 00 = triggered on negative level 01 = triggered on positive edge 10 = triggered on negative edge 11 = triggered on positive level
[1]
0
R/W
STAGE1_LOW_INT_EN
[2]
0
R/W
STAGE2_LOW_INT_EN
[3]
0
R/W
STAGE3_LOW_INT_EN
[4]
0
R/W
STAGE4_LOW_INT_EN
[5]
0
R/W
STAGE5_LOW_INT_EN
[6]
0
R/W
STAGE6_LOW_INT_EN
[7]
0
R/W
STAGE7_LOW_INT_EN
[11:8] [13:12]
0 0
R/W
Unused GPIO_SETUP
[15:14]
0
R/W
GPIO_INPUT_CONFIG
Rev. 0 | Page 38 of 56
AD7148
Table 23. STAGEx_HIGH_INT_EN Register
Address 0x006 Data Bit [0] Default Value 0 Type R/W Mnemonic STAGE0_HIGH_INT_EN Description STAGE0 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded STAGE1 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE1 high threshold is exceeded STAGE2 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE2 high threshold is exceeded STAGE3 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE3 high threshold is exceeded STAGE4 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE4 high threshold is exceeded STAGE5 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE5 high threshold is exceeded STAGE6 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE6 high threshold is exceeded STAGE7 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE7 high threshold is exceeded Set unused register bits to 0
[1]
0
R/W
STAGE1_HIGH_INT_EN
[2]
0
R/W
STAGE2_HIGH_INT_EN
[3]
0
R/W
STAGE3_HIGH_INT_EN
[4]
0
R/W
STAGE4_HIGH_INT_EN
[5]
0
R/W
STAGE5_HIGH_INT_EN
[6]
0
R/W
STAGE6_HIGH_INT_EN
[7]
0
R/W
STAGE7_HIGH_INT_EN
[15:8]
Unused
Rev. 0 | Page 39 of 56
AD7148
Table 24. STAGEx_COMPLETE_INT_EN Register
Address 0x007 Data Bit [0] Default Value 0 Type R/W Mnemonic STAGE0_COMPLETE_INT_EN Description STAGE0 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE0 conversion STAGE1 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE1 conversion STAGE2 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE2 conversion STAGE3 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE3 conversion STAGE4 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE4 conversion STAGE5 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE5 conversion STAGE6 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE6 conversion STAGE7 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE7 conversion Set unused register bits to 0
[1]
0
R/W
STAGE1_COMPLETE_INT_EN
[2]
0
R/W
STAGE2_COMPLETE_INT_EN
[3]
0
R/W
STAGE3_COMPLETE_INT_EN
[4]
0
R/W
STAGE4_COMPLETE_INT_EN
[5]
0
R/W
STAGE5_COMPLETE_INT_EN
[6]
0
R/W
STAGE6_COMPLETE_INT_EN
[7]
0
R/W
STAGE7_COMPLETE_INT_EN
[15:8]
Unused
Table 25. STAGEx_LOW_LIMIT_INT Register 1
Address 0x008 Data Bit [0] [1] [2] [3] [4] [5] [6] [7] [15:8]
1
Default Value 0 0 0 0 0 0 0 0
Type R R R R R R R R
Mnemonic STAGE0_LOW_LIMIT_INT STAGE1_LOW_LIMIT_INT STAGE2_LOW_LIMIT_INT STAGE3_LOW_LIMIT_INT STAGE4_LOW_LIMIT_INT STAGE5_LOW_LIMIT_INT STAGE6_LOW_LIMIT_INT STAGE7_LOW_LIMIT_INT Unused
Description STAGE0 CDC conversion low limit interrupt result 1 = indicates STAGE0_LOW_THRESHOLD value exceeded STAGE1 CDC conversion low limit interrupt result 1 = indicates STAGE1_LOW_THRESHOLD value exceeded STAGE2 CDC conversion low limit interrupt result 1 = indicates STAGE2_LOW_THRESHOLD value exceeded STAGE3 CDC conversion low limit interrupt result 1 = indicates STAGE3_LOW_THRESHOLD value exceeded STAGE4 CDC conversion low limit interrupt result 1 = indicates STAGE4_LOW_THRESHOLD value exceeded STAGE5 CDC conversion low limit interrupt result 1 = indicates STAGE5_LOW_THRESHOLD value exceeded STAGE6 CDC conversion low limit interrupt result 1 = indicates STAGE6_LOW_THRESHOLD value exceeded STAGE7 CDC conversion low limit interrupt result 1 = indicates STAGE7_LOW_THRESHOLD value exceeded Set unused register bits to 0
Registers self-clear to 0 after readback, provided that the limits are not exceeded.
Rev. 0 | Page 40 of 56
AD7148
Table 26. STAGEx_HIGH_LIMIT_INT Register 1
Address 0x009 Data Bit [0] [1] [2] [3] [4] [5] [6] [7] [15:8]
1
Default Value 0 0 0 0 0 0 0 0
Type R R R R R R R R
Mnemonic STAGE0_HIGH_LIMIT_INT STAGE1_HIGH_LIMIT_INT STAGE2_HIGH_LIMIT_INT STAGE3_HIGH_LIMIT_INT STAGE4_HIGH_LIMIT_INT STAGE5_HIGH_LIMIT_INT STAGE6_HIGH_LIMIT_INT STAGE7_HIGH_LIMIT_INT Unused
Description STAGE0 CDC conversion high limit interrupt result 1 = indicates STAGE0_HIGH_THRESHOLD value exceeded STAGE1 CDC conversion high limit interrupt result 1 = indicates STAGE1_HIGH_THRESHOLD value exceeded Stage2 CDC conversion high limit interrupt result 1 = indicates STAGE2_HIGH_THRESHOLD value exceeded STAGE3 CDC conversion high limit interrupt result 1 = indicates STAGE3_HIGH_THRESHOLD value exceeded STAGE4 CDC conversion high limit interrupt result 1 = indicates STAGE4_HIGH_THRESHOLD value exceeded STAGE5 CDC conversion high limit interrupt result 1 = indicates STAGE5_HIGH_THRESHOLD value exceeded STAGE6 CDC conversion high limit interrupt result 1 = indicates STAGE6_HIGH_THRESHOLD value exceeded STAGE7 CDC conversion high limit interrupt result 1 = indicates STAGE7_HIGH_THRESHOLD value exceeded Set unused register bits to 0
Registers self-clear to 0 after readback, provided that the limits are not exceeded.
Table 27. STAGEx_COMPLETE_INT_STATUS Register 1
Address 0x00A Data Bit [0] [1] [2] [3] [4] [5] [6] [7] [15:8]
1
Default Value 0 0 0 0 0 0 0 0
Type R R R R R R R R
Mnemonic STAGE0_COMPLETE_INT_STATUS STAGE1_COMPLETE_INT_STATUS STAGE2_COMPLETE_INT_STATUS STAGE3_COMPLETE_INT_STATUS STAGE4_COMPLETE_INT_STATUS STAGE5_COMPLETE_INT_STATUS STAGE6_COMPLETE_INT_STATUS STAGE7_COMPLETE_INT_STATUS Unused
Description STAGE0 conversion complete register interrupt status 1 = indicates STAGE0 conversion completed STAGE1 conversion complete register interrupt status 1 = indicates STAGE1 conversion completed STAGE2 conversion complete register interrupt status 1 = indicates STAGE2 conversion completed STAGE3 conversion complete register interrupt status 1 = indicates STAGE3 conversion completed STAGE4 conversion complete register interrupt status 1 = indicates STAGE4 conversion completed STAGE5 conversion complete register interrupt status 1 = indicates STAGE5 conversion completed STAGE6 conversion complete register interrupt status 1 = indicates STAGE6 conversion completed STAGE7 conversion complete register interrupt status 1 = indicates STAGE7 conversion completed Set unused register bits to 0
Registers self-clear to 0 after readback, provided that the limits are not exceeded.
Rev. 0 | Page 41 of 56
AD7148
Table 28. CDC 16-Bit Conversion Data Registers
Address 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value 0 0 0 0 0 0 0 0 Type R R R R R R R R Mnemonic CDC_RESULT_S0 CDC_RESULT_S1 CDC_RESULT_S2 CDC_RESULT_S3 CDC_RESULT_S4 CDC_RESULT_S5 CDC_RESULT_S6 CDC_RESULT_S7 Description STAGE0 CDC 16-bit conversion data STAGE1 CDC 16-bit conversion data STAGE2 CDC 16-bit conversion data STAGE3 CDC 16-bit conversion data STAGE4 CDC 16-bit conversion data STAGE5 CDC 16-bit conversion data STAGE6 CDC 16-bit conversion data STAGE7 CDC 16-bit conversion data
Table 29. Device ID Register
Address 0x017 Data Bit [3:0] [15:4] Default Value 0 148 Type R R Mnemonic REVISION_CODE DEVID Description AD7148 revision code AD7148 device ID = 0x148
Table 30. Proximity Status Register
Address 0x042 Data Bit [0] [1] [2] [3] [4] [5] [6] [7] [15:8] Default Value 0 0 0 0 0 0 0 0 Type R R R R R R R R Mnemonic STAGE0_PROXIMITY_STATUS STAGE1_PROXIMITY_STATUS STAGE2_PROXIMITY_STATUS STAGE3_PROXIMITY_STATUS STAGE4_PROXIMITY_STATUS STAGE5_PROXIMITY_STATUS STAGE6_PROXIMITY_STATUS STAGE7_PROXIMITY_STATUS Unused Description STAGE0 proximity status register 1 = indicates proximity has been detected on STAGE0 STAGE1 proximity status register 1 = indicates proximity has been detected on STAGE1 STAGE2 proximity status register 1 = indicates proximity has been detected on STAGE2 STAGE3 proximity status register 1 = indicates proximity has been detected on STAGE3 STAGE4 proximity status register 1 = indicates proximity has been detected on STAGE4 STAGE5 proximity status register 1 = indicates proximity has been detected on STAGE5 STAGE6 proximity status register 1 = indicates proximity has been detected on STAGE6 STAGE7 proximity status register 1 = indicates proximity has been detected on STAGE7 Set unused register bits to 0
Rev. 0 | Page 42 of 56
AD7148
BANK 2 REGISTERS
All address values are expressed in hexadecimal format.
Table 31. STAGE0 Configuration Registers
Address 0x080 0x081 0x082 0x083 0x084 0x085 0x086 0x087 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STAGE0_CONNECTION_SETUP[6:0] STAGE0_CONNECTION_SETUP[7] STAGE0_AFE_OFFSET STAGE0_SENSITIVITY STAGE0_OFFSET_LOW STAGE0_OFFSET_HIGH STAGE0_OFFSET_HIGH_CLAMP STAGE0_ OFFSET_LOW_CLAMP Description STAGE0 CIN[6:0] connection setup (see Table 39) STAGE0 CIN7 connection setup (see Table 40) STAGE0 AFE offset control (see Table 41) STAGE0 sensitivity control (see Table 42) STAGE0 initial offset low value STAGE0 initial offset high value STAGE0 offset high clamp value STAGE0 offset low clamp value
Table 32. STAGE1 Configuration Registers
Address 0x088 0x089 0x08A 0x08B 0x08C 0x08D 0x08E 0x08F Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STAGE1_CONNECTION_SETUP[6:0] STAGE1_CONNECTION_SETUP[7] STAGE1_AFE_OFFSET STAGE1_SENSITIVITY STAGE1_OFFSET_LOW STAGE1_OFFSET_HIGH STAGE1_OFFSET_HIGH_CLAMP STAGE1_OFFSET_LOW_CLAMP Description STAGE1 CIN[6:0] connection setup (see Table 39) STAGE1 CIN7 connection setup (see Table 40) STAGE1 AFE offset control (see Table 41) STAGE1 sensitivity control (see Table 42) STAGE1 initial offset low value STAGE1 initial offset high value STAGE1 offset high clamp value STAGE1 offset low clamp value
Table 33. STAGE2 Configuration Registers
Address 0x090 0x091 0x092 0x093 0x094 0x095 0x096 0x097 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STAGE2_CONNECTION_SETUP[6:0] STAGE2_CONNECTION_SETUP[7] STAGE2_AFE_OFFSET STAGE2_SENSITIVITY STAGE2_OFFSET_LOW STAGE2_OFFSET_HIGH STAGE2_OFFSET_HIGH_CLAMP STAGE2_OFFSET_LOW_CLAMP Description STAGE2 CIN[6:0] connection setup (see Table 39) STAGE2 CIN7 connection setup (see Table 40) STAGE2 AFE offset control (see Table 41) STAGE2 sensitivity control (see Table 42) STAGE2 initial offset low value STAGE2 initial offset high value STAGE2 offset high clamp value STAGE2 offset low clamp value
Rev. 0 | Page 43 of 56
AD7148
Table 34. STAGE3 Configuration Registers
Address 0x098 0x099 0x09A 0x09B 0x09C 0x09D 0x09E 0x09F Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STAGE3_CONNECTION_SETUP[6:0] STAGE3_CONNECTION_SETUP[7] STAGE3_AFE_OFFSET STAGE3_SENSITIVITY STAGE3_OFFSET_LOW STAGE3_OFFSET_HIGH STAGE3_OFFSET_HIGH_CLAMP STAGE3_OFFSET_LOW_CLAMP Description STAGE3 CIN[6:0] connection setup (see Table 39) STAGE3 CIN7 connection setup (see Table 40) STAGE3 AFE offset control (see Table 41) STAGE3 sensitivity control (see Table 42) STAGE3 initial offset low value STAGE3 initial offset high value STAGE3 offset high clamp value STAGE3 offset low clamp value
Table 35. STAGE4 Configuration Registers
Address 0x0A0 0x0A1 0x0A2 0x0A3 0x0A4 0x0A5 0x0A6 0x0A7 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STAGE4_CONNECTION_SETUP[6:0] STAGE4_CONNECTION_SETUP[7] STAGE4_AFE_OFFSET STAGE4_SENSITIVITY STAGE4_OFFSET_LOW STAGE4_OFFSET_HIGH STAGE4_OFFSET_HIGH_CLAMP STAGE4_OFFSET_LOW_CLAMP Description STAGE4 CIN[6:0] connection setup (see Table 39) STAGE4 CIN7 connection setup (see Table 40) STAGE4 AFE offset control (see Table 41) STAGE4 sensitivity control (see Table 42) STAGE4 initial offset low value STAGE4 initial offset high value STAGE4 offset high clamp value STAGE4 offset low clamp value
Table 36. STAGE5 Configuration Registers
Address 0x0A8 0x0A9 0x0AA 0x0AB 0x0AC 0x0AD 0x0AE 0x0AF Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE5_CONNECTION_SETUP[6:0] STAGE5_CONNECTION_SETUP[7] STAGE5_AFE_OFFSET STAGE5_SENSITIVITY STAGE5_OFFSET_LOW STAGE5_OFFSET_HIGH STAGE5_OFFSET_HIGH_CLAMP STAGE5_OFFSET_LOW_CLAMP Description STAGE5 CIN[6:0] connection setup (see Table 39) STAGE5 CIN7 connection setup (see Table 40) STAGE5 AFE offset control (see Table 41) STAGE5 sensitivity control (see Table 42) STAGE5 initial offset low value STAGE5 initial offset high value STAGE5 offset high clamp value STAGE5 offset low clamp value
Table 37. STAGE6 Configuration Registers
Address 0x0B0 0x0B1 0x0B2 0x0B3 0x0B4 0x0B5 0x0B6 0x0B7 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STAGE6_CONNECTION_SETUP[6:0] STAGE6_CONNECTION_SETUP[7] STAGE6_AFE_OFFSET STAGE6_SENSITIVITY STAGE6_OFFSET_LOW STAGE6_OFFSET_HIGH STAGE6_OFFSET_HIGH_CLAMP STAGE6_OFFSET_LOW_CLAMP Description STAGE6 CIN[6:0] connection setup (see Table 39) STAGE6 CIN7 connection setup (see Table 40) STAGE6 AFE offset control (see Table 41) STAGE6 sensitivity control (see Table 42) STAGE6 initial offset low value STAGE6 initial offset high value STAGE6 offset high clamp value STAGE6 offset low clamp value
Rev. 0 | Page 44 of 56
AD7148
Table 38. STAGE7 Configuration Registers
Address 0x0B8 0x0B9 0x0BA 0x0BB 0x0BC 0x0BD 0x0BE 0x0BF Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STAGE7_CONNECTION_SETUP[6:0] STAGE7_CONNECTION_SETUP[7] STAGE7_AFE_OFFSET STAGE7_SENSITIVITY STAGE7_OFFSET_LOW STAGE7_OFFSET_HIGH STAGE7_OFFSET_HIGH_CLAMP STAGE7_OFFSET_LOW_CLAMP Description STAGE7 CIN[6:0] connection setup (see Table 39) STAGE7 CIN7 connection setup (see Table 40) STAGE7 AFE offset control (see Table 41) STAGE7 sensitivity control (see Table 42) STAGE7 initial offset low value STAGE7 initial offset high value STAGE7 offset high clamp value STAGE7 offset low clamp value
Table 39. STAGEx Detailed CIN[0:6] Connection Setup Description (x = 0 to 7)
Data Bit [1:0] Default Value X Type R/W Mnemonic CIN0_CONNECTION_SETUP Description CIN0 connection setup 00 = CIN0 not connected to CDC inputs 01 = CIN0 connected to CDC negative input 10 = CIN0 connected to CDC positive input 11 = CIN0 connected to BIAS (connect unused CINx inputs) CIN1 connection setup 00 = CIN1 not connected to CDC inputs 01 = CIN1 connected to CDC negative input 10 = CIN1 connected to CDC positive input 11 = CIN1 connected to BIAS (connect unused CINx inputs) CIN2 connection setup 00 = CIN2 not connected to CDC inputs 01 = CIN2 connected to CDC negative input 10 = CIN2 connected to CDC positive input 11 = CIN2 connected to BIAS (connect unused CINx inputs) CIN3 connection setup 00 = CIN3 not connected to CDC inputs 01 = CIN3 connected to CDC negative input 10 = CIN3 connected to CDC positive input 11 = CIN3 connected to BIAS (connect unused CINx inputs) CIN4 connection setup 00 = CIN4 not connected to CDC inputs 01 = CIN4 connected to CDC negative input 10 = CIN4 connected to CDC positive input 11 = CIN4 connected to BIAS (connect unused CINx inputs) CIN5 connection setup 00 = CIN5 not connected to CDC inputs 01 = CIN5 connected to CDC negative input 10 = CIN5 connected to CDC positive input 11 = CIN5 connected to BIAS (connect unused CINx inputs) CIN6 connection setup 00 = CIN6 not connected to CDC inputs 01 = CIN6 connected to CDC negative input 10 = CIN6 connected to CDC positive input 11 = CIN6 connected to BIAS (connect unused CINx inputs) Set unused register bits to 0
[3:2]
X
R/W
CIN1_CONNECTION_SETUP
[5:4]
X
R/W
CIN2_CONNECTION_SETUP
[7:6]
X
R/W
CIN3_CONNECTION_SETUP
[9:8]
X
R/W
CIN4_CONNECTION_SETUP
[11:10]
X
R/W
CIN5_CONNECTION_SETUP
[13:12]
X
R/W
CIN6_CONNECTION_SETUP
[15:14]
X
Unused
Rev. 0 | Page 45 of 56
AD7148
Table 40. STAGEx Detailed CIN7 Connection Setup Description (x = 0 to 7)
Data Bit [1:0] Default Value X Type R/W Mnemonic CIN7_CONNECTION_SETUP Description CIN7 connection setup 00 = CIN7 not connected to CDC inputs 01 = CIN7 connected to CDC negative input 10 = CIN7 connected to CDC positive input 11 = CIN7 connected to BIAS (connect unused CINx inputs) Set unused register bits to 0 Single-ended measurement connection setup 00 = do not use 01 = use when one CIN is connected to CDC positive input, single-ended measurements only 10 = use when one CIN is connected to CDC negative input, single-ended measurements only 11 = differential connection to CDC Negative AFE offset enable control 0 = enable 1 = disable Positive AFE offset enable control 0 = enable 1 = disable
[12:2] [13:12]
X X R/W
Unused SE_CONNECTION_SETUP
[14]
X
R/W
NEG_AFE_OFFSET_DISABLE
[15]
X
R/W
POS_AFE_OFFSET_DISABLE
Table 41. STAGEx Detailed Offset Control Description (x = 0 to 7)
Data Bit [5:0] [6] [7] Default Value X X X Type R/W Mnemonic NEG_AFE_OFFSET Unused NEG_AFE_OFFSET_SWAP Description Negative AFE offset setting (20 pF range) 1 LSB value = 0.32 pF of offset Set to 0 Negative AFE offset swap control 0 = NEG_AFE_OFFSET applied to CDC negative input 1 = NEG_AFE_OFFSET applied to CDC positive input Positive AFE offset setting (20 pF range) 1 LSB value = 0.32 pF of offset Set to 0 Positive AFE offset swap control 0 = POS_AFE_OFFSET applied to CDC positive input 1 = POS_AFE_OFFSET applied to CDC negative input
R/W
[13:8] [14] [15]
X X X
R/W
POS_AFE_OFFSET Unused POS_AFE_OFFSET_SWAP
R/W
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Table 42. STAGEx Detailed Sensitivity Control Description (x = 0 to 7)
Data Bit [3:0] Default Value X Type R/W Mnemonic NEG_THRESHOLD_SENSITIVITY Description Negative threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.48%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% Negative peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level Set to 0 Positive threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.48%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% Positive peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level Set to 0
[6:4]
X
R/W
NEG_PEAK_DETECT
[7] [11:8]
X X
R/W
Unused POS_THRESHOLD_SENSITIVITY
[14:12]
X
R/W
POS_PEAK_DETECT
[15]
X
Unused
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BANK 3 REGISTERS
All address values are expressed in hexadecimal format.
Table 43. STAGE0 Results Registers
Address 0x0E0 0x0E1 0x0E2 0x0E3 0x0E4 0x0E5 0x0E6 0x0E7 0x0E8 0x0E9 0x0EA 0x0EB 0x0EC 0x0ED 0x0EE 0x0EF 0x0F0 0x0F1 0x0F2 0x0F3 0x0F4 0x0F5 0x0F6 0x0F7 0x0F8 0x0F9 0x0FA 0x0FB 0x0FC 0x0FD 0x0FE 0x0FF 0x100 0x101 0x102 0x103 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STAGE0_CONV_DATA STAGE0_FF_WORD0 STAGE0_FF_WORD1 STAGE0_FF_WORD2 STAGE0_FF_WORD3 STAGE0_FF_WORD4 STAGE0_FF_WORD5 STAGE0_FF_WORD6 STAGE0_FF_WORD7 STAGE0_SF_WORD0 STAGE0_SF_WORD1 STAGE0_SF_WORD2 STAGE0_SF_WORD3 STAGE0_SF_WORD4 STAGE0_SF_WORD5 STAGE0_SF_WORD6 STAGE0_SF_WORD7 STAGE0_SF_AMBIENT STAGE0_FF_AVG STAGE0_PEAK_DETECT_WORD0 STAGE0_PEAK_DETECT_WORD1 STAGE0_MAX_WORD0 STAGE0_MAX_WORD1 STAGE0_MAX_WORD2 STAGE0_MAX_WORD3 STAGE0_MAX_AVG STAGE0_HIGH_THRESHOLD STAGE0_MAX_TEMP STAGE0_MIN_WORD0 STAGE0_MIN_WORD1 STAGE0_MIN_WORD2 STAGE0_MIN_WORD3 STAGE0_MIN_AVG STAGE0_LOW_THRESHOLD STAGE0_MIN_TEMP Unused Description STAGE0 CDC 16-bit conversion data (copy of data in CDC_RESULT_S0 register) STAGE0 fast FIFO WORD0 STAGE0 fast FIFO WORD1 STAGE0 fast FIFO WORD2 STAGE0 fast FIFO WORD3 STAGE0 fast FIFO WORD4 STAGE0 fast FIFO WORD5 STAGE0 fast FIFO WORD6 STAGE0 fast FIFO WORD7 STAGE0 slow FIFO WORD0 STAGE0 slow FIFO WORD1 STAGE0 slow FIFO WORD2 STAGE0 slow FIFO WORD3 STAGE0 slow FIFO WORD4 STAGE0 slow FIFO WORD5 STAGE0 slow FIFO WORD6 STAGE0 slow FIFO WORD7 STAGE0 slow FIFO ambient value STAGE0 fast FIFO average value STAGE0 peak FIFO WORD0 value STAGE0 peak FIFO WORD1 value STAGE0 maximum value FIFO WORD0 STAGE0 maximum value FIFO WORD1 STAGE0 maximum value FIFO WORD2 STAGE0 maximum value FIFO WORD3 STAGE0 average maximum FIFO value STAGE0 high threshold value STAGE0 temporary maximum value STAGE0 minimum value FIFO WORD0 STAGE0 minimum value FIFO WORD1 STAGE0 minimum value FIFO WORD2 STAGE0 minimum value FIFO WORD3 STAGE0 average minimum FIFO value STAGE0 low threshold value STAGE0 temporary minimum value Set unused register bits to 0
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Table 44. STAGE1 Results Registers
Address 0x104 0x105 0x106 0x107 0x108 0x109 0x10A 0x10B 0x10C 0x10D 0x10E 0x10F 0x110 0x111 0x112 0x113 0x114 0x115 0x116 0x117 0x118 0x119 0x11A 0x11B 0x11C 0x11D 0x11E 0x11F 0x120 0x121 0x122 0x123 0x124 0x125 0x126 0x127 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STAGE1_CONV_DATA STAGE1_FF_WORD0 STAGE1_FF_WORD1 STAGE1_FF_WORD2 STAGE1_FF_WORD3 STAGE1_FF_WORD4 STAGE1_FF_WORD5 STAGE1_FF_WORD6 STAGE1_FF_WORD7 STAGE1_SF_WORD0 STAGE1_SF_WORD1 STAGE1_SF_WORD2 STAGE1_SF_WORD3 STAGE1_SF_WORD4 STAGE1_SF_WORD5 STAGE1_SF_WORD6 STAGE1_SF_WORD7 STAGE1_SF_AMBIENT STAGE1_FF_AVG STAGE1_CDC_WORD0 STAGE1_CDC_WORD1 STAGE1_MAX_WORD0 STAGE1_MAX_WORD1 STAGE1_MAX_WORD2 STAGE1_MAX_WORD3 STAGE1_MAX_AVG STAGE1_HIGH_THRESHOLD STAGE1_MAX_TEMP STAGE1_MIN_WORD0 STAGE1_MIN_WORD1 STAGE1_MIN_WORD2 STAGE1_MIN_WORD3 STAGE1_MIN_AVG STAGE1_LOW_THRESHOLD STAGE1_MIN_TEMP Unused Description STAGE1 CDC 16-bit conversion data (copy of data in CDC_RESULT_S1 register) STAGE1 fast FIFO WORD0 STAGE1 fast FIFO WORD1 STAGE1 fast FIFO WORD2 STAGE1 fast FIFO WORD3 STAGE1 fast FIFO WORD4 STAGE1 fast FIFO WORD5 STAGE1 fast FIFO WORD6 STAGE1 fast FIFO WORD7 STAGE1 slow FIFO WORD0 STAGE1 slow FIFO WORD1 STAGE1 slow FIFO WORD2 STAGE1 slow FIFO WORD3 STAGE1 slow FIFO WORD4 STAGE1 slow FIFO WORD5 STAGE1 slow FIFO WORD6 STAGE1 slow FIFO WORD7 STAGE1 slow FIFO ambient value STAGE1 fast FIFO average value STAGE1 CDC FIFO WORD0 STAGE1 CDC FIFO WORD1 STAGE1 maximum value FIFO WORD0 STAGE1 maximum value FIFO WORD1 STAGE1 maximum value FIFO WORD2 STAGE1 maximum value FIFO WORD3 STAGE1 average maximum FIFO value STAGE1 high threshold value STAGE1 temporary maximum value STAGE1 minimum value FIFO WORD0 STAGE1 minimum value FIFO WORD1 STAGE1 minimum value FIFO WORD2 STAGE1 minimum value FIFO WORD3 STAGE1 average minimum FIFO value STAGE1 low threshold value STAGE1 temporary minimum value Set unused register bits to 0
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Table 45. STAGE2 Results Registers
Address 0x128 0x129 0x12A 0x12B 0x12C 0x12D 0x12E 0x12F 0x130 0x131 0x132 0x133 0x134 0x135 0x136 0x137 0x138 0x139 0x13A 0x13B 0x13C 0x13D 0x13E 0x13F 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x148 0x148 0x149 0x14A 0x14B Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STAGE2_CONV_DATA STAGE2_FF_WORD0 STAGE2_FF_WORD1 STAGE2_FF_WORD2 STAGE2_FF_WORD3 STAGE2_FF_WORD4 STAGE2_FF_WORD5 STAGE2_FF_WORD6 STAGE2_FF_WORD7 STAGE2_SF_WORD0 STAGE2_SF_WORD1 STAGE2_SF_WORD2 STAGE2_SF_WORD3 STAGE2_SF_WORD4 STAGE2_SF_WORD5 STAGE2_SF_WORD6 STAGE2_SF_WORD7 STAGE2_SF_AMBIENT STAGE2_FF_AVG STAGE2_CDC_WORD0 STAGE2_CDC_WORD1 STAGE2_MAX_WORD0 STAGE2_MAX_WORD1 STAGE2_MAX_WORD2 STAGE2_MAX_WORD3 STAGE2_MAX_AVG STAGE2_HIGH_THRESHOLD STAGE2_MAX_TEMP STAGE2_MIN_WORD0 STAGE2_MIN_WORD1 STAGE2_MIN_WORD2 STAGE2_MIN_WORD3 STAGE2_MIN_AVG STAGE2_LOW_THRESHOLD STAGE2_MIN_TEMP Unused Description STAGE2 CDC 16-bit conversion data (copy of data in CDC_RESULT_S2 register) STAGE2 fast FIFO WORD0 STAGE2 fast FIFO WORD1 STAGE2 fast FIFO WORD2 STAGE2 fast FIFO WORD3 STAGE2 fast FIFO WORD4 STAGE2 fast FIFO WORD5 STAGE2 fast FIFO WORD6 STAGE2 fast FIFO WORD7 STAGE2 slow FIFO WORD0 STAGE2 slow FIFO WORD1 STAGE2 slow FIFO WORD2 STAGE2 slow FIFO WORD3 STAGE2 slow FIFO WORD4 STAGE2 slow FIFO WORD5 STAGE2 slow FIFO WORD6 STAGE2 slow FIFO WORD7 STAGE2 slow FIFO ambient value STAGE2 fast FIFO average value STAGE2 CDC FIFO WORD0 STAGE2 CDC FIFO WORD1 STAGE2 maximum value FIFO WORD0 STAGE2 maximum value FIFO WORD1 STAGE2 maximum value FIFO WORD2 STAGE2 maximum value FIFO WORD3 STAGE2 average maximum FIFO value STAGE2 high threshold value STAGE2 temporary maximum value STAGE2 minimum value FIFO WORD0 STAGE2 minimum value FIFO WORD1 STAGE2 minimum value FIFO WORD2 STAGE2 minimum value FIFO WORD3 STAGE2 average minimum FIFO value STAGE2 low threshold value STAGE2 temporary minimum value Set unused register bits to 0
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Table 46. STAGE3 Results Registers
Address 0x14C 0x14D 0x14E 0x14F 0x150 0x151 0x152 0x153 0x154 0x155 0x156 0x157 0x158 0x159 0x15A 0x15B 0x15C 0x15D 0x15E 0x15F 0x160 0x161 0x162 0x163 0x164 0x165 0x166 0x167 0x168 0x169 0x16A 0x16B 0x16C 0x16D 0x16E 0x16F Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STAGE3_CONV_DATA STAGE3_FF_WORD0 STAGE3_FF_WORD1 STAGE3_FF_WORD2 STAGE3_FF_WORD3 STAGE3_FF_WORD4 STAGE3_FF_WORD5 STAGE3_FF_WORD6 STAGE3_FF_WORD7 STAGE3_SF_WORD0 STAGE3_SF_WORD1 STAGE3_SF_WORD2 STAGE3_SF_WORD3 STAGE3_SF_WORD4 STAGE3_SF_WORD5 STAGE3_SF_WORD6 STAGE3_SF_WORD7 STAGE3_SF_AMBIENT STAGE3_FF_AVG STAGE3_CDC_WORD0 STAGE3_CDC_WORD1 STAGE3_MAX_WORD0 STAGE3_MAX_WORD1 STAGE3_MAX_WORD2 STAGE3_MAX_WORD3 STAGE3_MAX_AVG STAGE3_HIGH_THRESHOLD STAGE3_MAX_TEMP STAGE3_MIN_WORD0 STAGE3_MIN_WORD1 STAGE3_MIN_WORD2 STAGE3_MIN_WORD3 STAGE3_MIN_AVG STAGE3_LOW_THRESHOLD STAGE3_MIN_TEMP Unused Description STAGE3 CDC 16-bit conversion data (copy of data in CDC_RESULT_S3 register) STAGE3 fast FIFO WORD0 STAGE3 fast FIFO WORD1 STAGE3 fast FIFO WORD2 STAGE3 fast FIFO WORD3 STAGE3 fast FIFO WORD4 STAGE3 fast FIFO WORD5 STAGE3 fast FIFO WORD6 STAGE3 fast FIFO WORD7 STAGE3 slow FIFO WORD0 STAGE3 slow FIFO WORD1 STAGE3 slow FIFO WORD2 STAGE3 slow FIFO WORD3 STAGE3 slow FIFO WORD4 STAGE3 slow FIFO WORD5 STAGE3 slow FIFO WORD6 STAGE3 slow FIFO WORD7 STAGE3 slow FIFO ambient value STAGE3 fast FIFO average value STAGE3 CDC FIFO WORD0 STAGE3 CDC FIFO WORD1 STAGE3 maximum value FIFO WORD0 STAGE3 maximum value FIFO WORD1 STAGE3 maximum value FIFO WORD2 STAGE3 maximum value FIFO WORD3 STAGE3 average maximum FIFO value STAGE3 high threshold value STAGE3 temporary maximum value STAGE3 minimum value FIFO WORD0 STAGE3 minimum value FIFO WORD1 STAGE3 minimum value FIFO WORD2 STAGE3 minimum value FIFO WORD3 STAGE3 average minimum FIFO value STAGE3 low threshold value STAGE3 temporary minimum value Set unused register bits to 0
Rev. 0 | Page 51 of 56
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Table 47. STAGE4 Results Registers
Address 0x170 0x171 0x172 0x173 0x174 0x175 0x176 0x177 0x178 0x179 0x17A 0x17B 0x17C 0x17D 0x17E 0x17F 0x180 0x181 0x182 0x183 0x184 0x185 0x186 0x187 0x188 0x189 0x18A 0x18B 0x18C 0x18D 0x18E 0x18F 0x190 0x191 0x192 0x193 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STAGE4_CONV_DATA STAGE4_FF_WORD0 STAGE4_FF_WORD1 STAGE4_FF_WORD2 STAGE4_FF_WORD3 STAGE4_FF_WORD4 STAGE4_FF_WORD5 STAGE4_FF_WORD6 STAGE4_FF_WORD7 STAGE4_SF_WORD0 STAGE4_SF_WORD1 STAGE4_SF_WORD2 STAGE4_SF_WORD3 STAGE4_SF_WORD4 STAGE4_SF_WORD5 STAGE4_SF_WORD6 STAGE4_SF_WORD7 STAGE4_SF_AMBIENT STAGE4_FF_AVG STAGE4_CDC_WORD0 STAGE4_CDC_WORD1 STAGE4_MAX_WORD0 STAGE4_MAX_WORD1 STAGE4_MAX_WORD2 STAGE4_MAX_WORD3 STAGE4_MAX_AVG STAGE4_HIGH_THRESHOLD STAGE4_MAX_TEMP STAGE4_MIN_WORD0 STAGE4_MIN_WORD1 STAGE4_MIN_WORD2 STAGE4_MIN_WORD3 STAGE4_MIN_AVG STAGE4_LOW_THRESHOLD STAGE4_MIN_TEMP Unused Description STAGE4 CDC 16-bit conversion data (copy of data in CDC_RESULT_S4 register) STAGE4 fast FIFO WORD0 STAGE4 fast FIFO WORD1 STAGE4 fast FIFO WORD2 STAGE4 fast FIFO WORD3 STAGE4 fast FIFO WORD4 STAGE4 fast FIFO WORD5 STAGE4 fast FIFO WORD6 STAGE4 fast FIFO WORD7 STAGE4 slow FIFO WORD0 STAGE4 slow FIFO WORD1 STAGE4 slow FIFO WORD2 STAGE4 slow FIFO WORD3 STAGE4 slow FIFO WORD4 STAGE4 slow FIFO WORD5 STAGE4 slow FIFO WORD6 STAGE4 slow FIFO WORD7 STAGE4 slow FIFO ambient value STAGE4 fast FIFO average value STAGE4 CDC FIFO WORD0 STAGE4 CDC FIFO WORD1 STAGE4 maximum value FIFO WORD0 STAGE4 maximum value FIFO WORD1 STAGE4 maximum value FIFO WORD2 STAGE4 maximum value FIFO WORD3 STAGE4 average maximum FIFO value STAGE4 high threshold value STAGE4 temporary maximum value STAGE4 minimum value FIFO WORD0 STAGE4 minimum value FIFO WORD1 STAGE4 minimum value FIFO WORD2 STAGE4 minimum value FIFO WORD3 STAGE4 average minimum FIFO value STAGE4 low threshold value STAGE4 temporary minimum value Set unused register bits to 0
Rev. 0 | Page 52 of 56
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Table 48. STAGE5 Results Registers
Address 0x194 0x195 0x196 0x197 0x198 0x199 0x19A 0x19B 0x19C 0x19D 0x19E 0x19F 0x1A0 0x1A1 0x1A2 0x1A3 0x1A4 0x1A5 0x1A6 0x1A7 0x1A8 0x1A9 0x1AA 0x1AB 0x1AC 0x1AD 0x1AE 0x1AF 0x1B0 0x1B1 0x1B2 0x1B3 0x1B4 0x1B5 0x1B6 0x1B7 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STAGE5_CONV_DATA STAGE5_FF_WORD0 STAGE5_FF_WORD1 STAGE5_FF_WORD2 STAGE5_FF_WORD3 STAGE5_FF_WORD4 STAGE5_FF_WORD5 STAGE5_FF_WORD6 STAGE5_FF_WORD7 STAGE5_SF_WORD0 STAGE5_SF_WORD1 STAGE5_SF_WORD2 STAGE5_SF_WORD3 STAGE5_SF_WORD4 STAGE5_SF_WORD5 STAGE5_SF_WORD6 STAGE5_SF_WORD7 STAGE5_SF_AMBIENT STAGE5_FF_AVG STAGE5_CDC_WORD0 STAGE5_CDC_WORD1 STAGE5_MAX_WORD0 STAGE5_MAX_WORD1 STAGE5_MAX_WORD2 STAGE5_MAX_WORD3 STAGE5_MAX_AVG STAGE5_HIGH_THRESHOLD STAGE5_MAX_TEMP STAGE5_MIN_WORD0 STAGE5_MIN_WORD1 STAGE5_MIN_WORD2 STAGE5_MIN_WORD3 STAGE5_MIN_AVG STAGE5_LOW_THRESHOLD STAGE5_MIN_TEMP Unused Description STAGE5 CDC 16-bit conversion data (copy of data in CDC_RESULT_S5 register) STAGE5 fast FIFO WORD0 STAGE5 fast FIFO WORD1 STAGE5 fast FIFO WORD2 STAGE5 fast FIFO WORD3 STAGE5 fast FIFO WORD4 STAGE5 fast FIFO WORD5 STAGE5 fast FIFO WORD6 STAGE5 fast FIFO WORD7 STAGE5 slow FIFO WORD0 STAGE5 slow FIFO WORD1 STAGE5 slow FIFO WORD2 STAGE5 slow FIFO WORD3 STAGE5 slow FIFO WORD4 STAGE5 slow FIFO WORD5 STAGE5 slow FIFO WORD6 STAGE5 slow FIFO WORD7 STAGE5 slow FIFO ambient value STAGE5 fast FIFO average value STAGE5 CDC FIFO WORD0 STAGE5 CDC FIFO WORD1 STAGE5 maximum value FIFO WORD0 STAGE5 maximum value FIFO WORD1 STAGE5 maximum value FIFO WORD2 STAGE5 maximum value FIFO WORD3 STAGE5 average maximum FIFO value STAGE5 high threshold value STAGE5 temporary maximum value STAGE5 minimum value FIFO WORD0 STAGE5 minimum value FIFO WORD1 STAGE5 minimum value FIFO WORD2 STAGE5 minimum value FIFO WORD3 STAGE5 average minimum FIFO value STAGE5 low threshold value STAGE5 temporary minimum value Set unused register bits to 0
Rev. 0 | Page 53 of 56
AD7148
Table 49. STAGE6 Results Registers
Address 0x1B8 0x1B9 0x1BA 0x1BB 0x1BC 0x1BD 0x1BE 0x1BF 0x1C0 0x1C1 0x1C2 0x1C3 0x1C4 0x1C5 0x1C6 0x1C7 0x1C8 0x1C9 0x1CA 0x1CB 0x1CC 0x1CD 0x1CE 0x1CF 0x1D0 0x1D1 0x1D2 0x1D3 0x1D4 0x1D5 0x1D6 0x1D7 0x1D8 0x1D9 0x1DA 0x1DB Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STAGE6_CONV_DATA STAGE6_FF_WORD0 STAGE6_FF_WORD1 STAGE6_FF_WORD2 STAGE6_FF_WORD3 STAGE6_FF_WORD4 STAGE6_FF_WORD5 STAGE6_FF_WORD6 STAGE6_FF_WORD7 STAGE6_SF_WORD0 STAGE6_SF_WORD1 STAGE6_SF_WORD2 STAGE6_SF_WORD3 STAGE6_SF_WORD4 STAGE6_SF_WORD5 STAGE6_SF_WORD6 STAGE6_SF_WORD7 STAGE6_SF_AMBIENT STAGE6_FF_AVG STAGE6_CDC_WORD0 STAGE6_CDC_WORD1 STAGE6_MAX_WORD0 STAGE6_MAX_WORD1 STAGE6_MAX_WORD2 STAGE6_MAX_WORD3 STAGE6_MAX_AVG STAGE6_HIGH_THRESHOLD STAGE6_MAX_TEMP STAGE6_MIN_WORD0 STAGE6_MIN_WORD1 STAGE6_MIN_WORD2 STAGE6_MIN_WORD3 STAGE6_MIN_AVG STAGE6_LOW_THRESHOLD STAGE6_MIN_TEMP Unused Description STAGE6 CDC 16-bit conversion data (copy of data in CDC_RESULT_S6 register) STAGE6 fast FIFO WORD0 STAGE6 fast FIFO WORD1 STAGE6 fast FIFO WORD2 STAGE6 fast FIFO WORD3 STAGE6 fast FIFO WORD4 STAGE6 fast FIFO WORD5 STAGE6 fast FIFO WORD6 STAGE6 fast FIFO WORD7 STAGE6 slow FIFO WORD0 STAGE6 slow FIFO WORD1 STAGE6 slow FIFO WORD2 STAGE6 slow FIFO WORD3 STAGE6 slow FIFO WORD4 STAGE6 slow FIFO WORD5 STAGE6 slow FIFO WORD6 STAGE6 slow FIFO WORD7 STAGE6 slow FIFO ambient value STAGE6 fast FIFO average value STAGE0 CDC FIFO WORD0 STAGE6 CDC FIFO WORD1 STAGE6 maximum value FIFO WORD0 STAGE6 maximum value FIFO WORD1 STAGE6 maximum value FIFO WORD2 STAGE6 maximum value FIFO WORD3 STAGE6 average maximum FIFO value STAGE6 high threshold value STAGE6 temporary maximum value STAGE6 minimum value FIFO WORD0 STAGE6 minimum value FIFO WORD1 STAGE6 minimum value FIFO WORD2 STAGE6 minimum value FIFO WORD3 STAGE6 average minimum FIFO value STAGE6 low threshold value STAGE6 temporary minimum value Set unused register bits to 0
Rev. 0 | Page 54 of 56
AD7148
Table 50. STAGE7 Results Registers
Address 0x1DC 0x1DD 0x1DE 0x1DF 0x1E0 0x1E1 0x1E2 0x1E3 0x1E4 0x1E5 0x1E6 0x1E7 0x1E8 0x1E9 0x1EA 0x1EB 0x1EC 0x1ED 0x1EE 0x1EF 0x1F0 0x1F1 0x1F2 0x1F3 0x1F4 0x1F5 0x1F6 0x1F7 0x1F8 0x1F9 0x1FA 0x1FB 0x1FC 0x1FD 0x1FE 0x1FF Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STAGE7_CONV_DATA STAGE7_FF_WORD0 STAGE7_FF_WORD1 STAGE7_FF_WORD2 STAGE7_FF_WORD3 STAGE7_FF_WORD4 STAGE7_FF_WORD5 STAGE7_FF_WORD6 STAGE7_FF_WORD7 STAGE7_SF_WORD0 STAGE7_SF_WORD1 STAGE7_SF_WORD2 STAGE7_SF_WORD3 STAGE7_SF_WORD4 STAGE7_SF_WORD5 STAGE7_SF_WORD6 STAGE7_SF_WORD7 STAGE7_SF_AMBIENT STAGE7_FF_AVG STAGE7_CDC_WORD0 STAGE7_CDC_WORD1 STAGE7_MAX_WORD0 STAGE7_MAX_WORD1 STAGE7_MAX_WORD2 STAGE7_MAX_WORD3 STAGE7_MAX_AVG STAGE7_HIGH_THRESHOLD STAGE7_MAX_TEMP STAGE7_MIN_WORD0 STAGE7_MIN_WORD1 STAGE7_MIN_WORD2 STAGE7_MIN_WORD3 STAGE7_MIN_AVG STAGE7_LOW_THRESHOLD STAGE7_MIN_TEMP Unused Description STAGE7 CDC 16-bit conversion data (copy of data in CDC_RESULT_S7 register) STAGE7 fast FIFO WORD0 STAGE7 fast FIFO WORD1 STAGE7 fast FIFO WORD2 STAGE7 fast FIFO WORD3 STAGE7 fast FIFO WORD4 STAGE7 fast FIFO WORD5 STAGE7 fast FIFO WORD6 STAGE7 fast FIFO WORD7 STAGE7 slow FIFO WORD0 STAGE7 slow FIFO WORD1 STAGE7 slow FIFO WORD2 STAGE7 slow FIFO WORD3 STAGE7 slow FIFO WORD4 STAGE7 slow FIFO WORD5 STAGE7 slow FIFO WORD6 STAGE7 slow FIFO WORD7 STAGE7 slow FIFO ambient value STAGE7 fast FIFO average value STAGE7 CDC FIFO WORD0 STAGE7 CDC FIFO WORD1 STAGE7 maximum value FIFO WORD0 STAGE7 maximum value FIFO WORD1 STAGE7 maximum value FIFO WORD2 STAGE7 maximum value FIFO WORD3 STAGE7 average maximum FIFO value STAGE7 high threshold value STAGE7 temporary maximum value STAGE7 minimum value FIFO WORD0 STAGE7 minimum value FIFO WORD1 STAGE7 minimum value FIFO WORD2 STAGE7 minimum value FIFO WORD3 STAGE7 average minimum FIFO value STAGE7 low threshold value STAGE7 temporary minimum value Set unused register bits to 0
Rev. 0 | Page 55 of 56
AD7148 OUTLINE DIMENSIONS
4.00 BSC SQ 0.60 MAX 0.50 0.40 0.30
PIN 1 INDICATOR
12 13
16
1
PIN 1 INDICATOR
3.75 BSC SQ 0.65 BSC TOP VIEW
9
EXPOSED PAD
4 8 5
2.65 2.50 SQ 2.35 0.25 MIN
1.95 BSC 0.80 MAX 0.65 TYP BOT TOM VIEW
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC.
Figure 47. 16-Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Very Thin Quad (CP-16-13) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7148ACPZ-1REEL1 AD7148ACPZ-1500RL71
1
Temperature Range -40C to +85C -40C to +85C
Serial Interface Description I2C Interface I2C Interface
Package Description 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ
122107-A
12 MAX 1.00 0.85 0.80 SEATING 0.30 PLANE 0.23 0.18
0.05 MAX 0.02 NOM COPLANARITY 0.20 REF 0.08
Package Option CP-16-13 CP-16-13
Z = RoHS Compliant Part.
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07155-0-12/07(0)
Rev. 0 | Page 56 of 56

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